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MPC99J93 Dataheets PDF



Part Number MPC99J93
Manufacturers Motorola
Logo Motorola
Description Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver
Datasheet MPC99J93 DatasheetMPC99J93 Datasheet (PDF)

MOTOROLA Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc. Order Number: MPC99J93/D Rev 1, 08/2003 Product Preview Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs g.

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MOTOROLA Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc. Order Number: MPC99J93/D Rev 1, 08/2003 Product Preview Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. Features: • Fully Integrated PLL MPC99J93 Freescale Semiconductor, Inc... FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A • • • • • Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32--Lead LQFP Packaging Functional Description The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section). PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR OR Dynamic Switch Logic Qb0 Qb0 Qb1 Qb1 ÷2 PLL 200 -- 360 MHz ÷4 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 Figure 1. Block Diagram This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. E Motorola Inc. 2003 MOTOROLA TIMING SOLUTIONS 1 For More Information On This Product, Go to: www.freescale.com MPC99J93 Freescale Semiconductor, Inc. VCC VCC 17 16 15 14 VCC Inp0bad Inp1bad Clk_Selected GND Ext_FB Ext_FB GND 13 12 11 10 9 1 2 3 4 5 6 7 8 GND Qb0 Qb0 Qb1 Qb1 Qb2 19 CLK1 Qb2 18 CLK1 24 Qa1 Qa1 Qa0 Qa0 VCC VCC_PLL Man_Override 25 26 27 28 29 30 31 32 23 22 21 20 MPC99J93 Freescale Semiconductor, Inc... PLL_En Alarm_Reset CLK0 CLK0 Figure 2. 32-Lead Pinout (Top View) Table 1. Pin Descriptions Pin Name CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa0:1, Qa0:1 Qb0:2, Qb0:2 Inp0bad Inp1bad Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND I/O LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input Power Supply Power Supply Power Supply Power Supply Pin Definition Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Differential 1x output pairs. Connect one QAx pair to Ext_FB. Differential 2x output pairs Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted ‘0’ if clock 0 is selected, ‘1’ if clock 1 is selected ‘0’ will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one--shotted” (50kΩ pullup) ‘0’ selects CLK0, ‘1’ selects CLK1 (50kΩ pulldown) ‘1’ disables internal clock switch circuitry (50kΩ pulldown) ‘0’ bypasses selected input reference around the phase--locked loop (50kΩ pullup) ‘0’ resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50kΩ pullup) PLL power supply Digital power supply PLL ground Digital ground 2 Sel_Clk MR MOTOROLA TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 2. ABSOLUTE MAXIMUM RATINGSa Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 ±20 ±50 125 Unit V V V mA mA °C MPC99J93 Condition a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. GENERAL SPECIFICATIONS Symbol Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model Latch-up immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board 175 1500 1000 100 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V V mA pF °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Input.


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