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MB84VA2006 Dataheets PDF



Part Number MB84VA2006
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description (MB84VA2006 / MB84VA2007) 8M (x 8/x 16) FLASH MEMORY & 1M (x 8) STATIC RAM
Datasheet MB84VA2006 DatasheetMB84VA2006 Datasheet (PDF)

FUJITSU SEMICONDUCTOR DATA SHEET DS05-50107-1E MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 8M (× 8/× 16) FLASH MEMORY & 1M (× 8) STATIC RAM MB84VA2006-10/MB84VA2007-10 s FEATURES • Power supply voltage of 2.7 to 3.6 V • High performance 100 ns maximum access time • Operating Temperature –20 to +85°C — FLASH MEMORY • Minimum 100,000 write/erase cycles • Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. Any combination of sectors can be concurr.

  MB84VA2006   MB84VA2006



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FUJITSU SEMICONDUCTOR DATA SHEET DS05-50107-1E MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 8M (× 8/× 16) FLASH MEMORY & 1M (× 8) STATIC RAM MB84VA2006-10/MB84VA2007-10 s FEATURES • Power supply voltage of 2.7 to 3.6 V • High performance 100 ns maximum access time • Operating Temperature –20 to +85°C — FLASH MEMORY • Minimum 100,000 write/erase cycles • Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VA2006: Top sector MB84VA2007: Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Please refer to "MBM29LV800TA/BA" data sheet in detailed function — SRAM • Power dissipation Operating : 35 mA max. Standby : 30 µA max. • Power down features using CE1s and CE2s • Data retention supply voltage: 2.0 V to 3.6 V Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. MB84VA2006-10/MB84VA2007-10 s BLOCK DIAGRAM VCCf A0 to A18 A0 to A18 A-1 RESET CEf BYTE 8 M bit Flash Memory VSS RY/BY DQ8 to DQ15 DQ0 to DQ7 VCCs A0 to A15 VSS SA WE OE CE1s CE2s 1 M bit Static RAM s EXAMPLE OF CONNECTION WITH CHIPSET VCC A[0:19] A[1:19] A0 A[0:18] SA VCCf BYTE RESET ROM_CS/ RAM_CS/ Battery Backup Control BATTERY BACKUP HWR/ LWR/ RD/ D[0:15] D[0:15] CHIPSET CEf CE1s RY/BY VCCs CE2s WE OE DQ[0:15] MB84VA2006/7 2 MB84VA2006-10/MB84VA2007-10 s PIN ASSIGNMENTS (Top View) A 6 5 4 3 2 1 CE1s A10 OE A11 A13 WE B VSS DQ5 DQ7 A8 A17 VCCs C DQ1 DQ2 DQ4 A5 SA* A16 D A1 A0 DQ0 DQ8 CEf VSS E A2 A3 A6 DQ3 DQ10 DQ9 F A4 A7 A18 DQ12 VCCf DQ11 G CE2s RY/BY RESET A12 DQ6 DQ13 H A9 A14 A15 BYTE DQ15/A-1 DQ14 *: A16 for SRAM Table 1 Pin Configuration Pin A0 to A15 A-1, A16 to A18 SA DQ0 to DQ7 DQ8 to DQ15 CEf CE1s CE2s OE WE RY/BY BYTE RESET N.C. VSS VCCf VCCs Function Address Inputs (Common) Address Input (Flash) Address Input (SRAM) Data Inputs/Outputs (Common) Data Inputs/Outputs (Flash) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Selects 8-bit or 16-bit mode (Flash) Hardware Reset Pin/Sector Protection Unlock (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM) Input/ Output I I I I/O I/O I I I I I O I I — Power Power Power 3 MB84VA2006-10/MB84VA2007-10 s PRODUCT LINE UP Flash Memory Ordering Part No. VCC = 3.0 V +0.6 V –0.3 V SRAM MB84VA2006-10/MB84VA2007-10 100 100 40 100 100 50 Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) s BUS OPERATIONS Table 2 User Bus Operations (BYTE=VIL) Operation (1), (3) Full Standby Output Disable Read from Flash (2) Write to Flash Read from SRAM Write to SRAM Flash Hardware Reset CEf H X L L H H X CE1s H X X H X H X L L H X CE2s X L X X L X L H H X L OE X H L H L X X WE X H H L H L X DQ0 to DQ7 DQ8 to DQ15 HIGH-Z HIGH-Z DOUT DIN DOUT DIN HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z RESET H H H H H H L Table 3 User Bus Operations (BYTE=VIH) Operation (1), (3) Full Standby Output Disable Read from Flash (2) CEf H X L CE1s H X X H X H X L L H X CE2s X L X X L X L H H X L OE X H L WE X H H DQ0 to DQ7 DQ8 to DQ15 HIGH-Z HIGH-Z DOUT HIGH-Z HIGH-Z DOUT RESET H H H Write to Flash Read from SRAM Write to SRAM Flash Hardware Reset L H H X H L X X L H L X DIN DOUT DIN HIGH-Z DIN HIGH-Z HIGH-Z HIGH-Z H H H L Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Notes: 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 4. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4 MB84VA2006-10/MB84VA2007-10 s FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY • One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. • Individual-sector, multiple-sector, or bulk-erase capability. (×8) FFFFFH 16K byte FC000H 8K byte FA000H 8K byte F8000H 32K byte F0000H 64K byte E0000H 64K byte D0000H 64K byte C0000H 64K byte B0000H 64K byte A0000H 64K byte 90000H 64K byte 80000H 64K byte 70000H 64K byte 60000H 64K byte 50000H 64K byte 40000H 64K byte 30000H 64K byte 20000H 64K byte 10000H 64K byte 00000H MB84VA2006 Sector Architecture (×16) 7FFFFH 64K byte 7E000H 64K byte 7D000H 64K byte 7C000H 64K byte 78000H 64K b.


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