ICS508

PRELIMINARY INFORMATION ICS508 PECL to CMOS Converter Description The ICS508 is the most cost effective way to generate a high quality, high frequency CMOS clock output from a PECL clock input. The ICS508 has separate VDD supplies for the PECL input buffer and the output buffer allowing different voltages to be used. For example, the input clock could use a 3.3 V supply while the output operates from 2.5 V. The device has an Output Enable pin that tri-states the clock output when the OE pin is taken low. The ICS508 is a member of the ClockBlocks™ family of devices. Features Packaged as 8 pin SOIC or die Separate VDD supplies allow voltage translation Clock frequency of 0 - 250 MHz Duty cycle of 45/55 Operating voltages of 2.375 to 5.5 V Tri-state output for board level testing 24 mA drive capability Industrial temperature version available Advanced, low power CMOS process Block Diagram VDDP VDDC PECLIN PECLIN Output Buffer CLK GND OE GND 1 Revision 012400 Printed 11/13/00 Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com MDS 508 C PRELIMINARY INFORMATION ICS508 PECL to CMOS Converter Pin Assignment VDDP PECLIN PECLIN GND 1 2 3 4 8 7 6 5 VDDC CLK GND OE Pin Descriptions Number 1 2 3 4 5 6 7 8 Name VDDP PECLIN PECLIN GND OE GND CLK VDDC Type O I I P I P O P Description Connect to 3.3 V or 5 V. Supplies PECL input buffer. Complementary PECL clock input. PECL clock input. Connect to ground. O...