Document
HA13631T
CD-ROM Combo Driver
ADE-207-320 (Z) 1st Edition Feb. 2000 Description
The HA13631T is combination of Spindle, Forcus, Tracking, Slide, Tray designed for CD-ROM and have following functions and features.
Functions
• • • • • • 1.5 A spindle driver 0.75 A focus driver 0.75 A tracking driver 1.0 A slide driver 0.75 A tray driver Over temperature shut down (OTSD)
Features
• • • • • Corresponds to both of sensor motor and sensorless motor All direct PWM drive Low on resistance Low power dissipation Small thin surface mount package
HA13631T
Pin Arrangement
ASGND SLDIN OP3IN OP4IN VSLD TRYIN SLDP SLDN SLDGND VTRY TRYP TRYN BSTGND BP1 BP2 VBST U RNF V W EXTCOM FGOUT COMM BRKSEL CE HB HU+ ASGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (Top view) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ASGND NC NC OP1IN FCSIN FCSN FCSP VFCS FCSGND TRKP TRKN TRKIN OP2IN VSS SGND PWMDC CT2 CT1 RT REFIN VCTL HWHW+ HVHV+ HUVSPN ASGND
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HA13631T
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Pin Name ASGND SLDIN OP3IN OP4IN VSLD TRYIN SLDP SLDN SLDGND VTRY TRYP TRYN BSTGND BP1 BP2 VBST U RNF V W EXTCOM FGOUT COMM BRKSEL CE HB HU+ ASGND ASGND VSPN HU– HV+ HV– Function Actuator small signal GND SLD driver control input Inverted input of OP amp. 3 for SLD driver control Inverted input of OP amp. 4 for TRY driver control SLD driver power supply TRY driver control input SLD driver P output SLD driver N output SLD and TRY driver GND TRY driver power supply TRY driver P output TRY driver N output Booster GND Booster pumping capacitor connection Booster pumping capacitor connection Booster output pin. This circuit generates a voltage about two times of the VSPN pin. U phase output SPN driver current detection V phase output W phase output COMM signal on/off control and FGOUT switching. (Refer to the Timing Chart) FG output (Refer to the Timing Chart) open drain Start-up clock input pin for sensorless (Refer to the Timing Chart) To select the brake mode (Refer to the Truth Table) Chip enable (Refer to the Truth Table) Hall bias switch U-phase Hall +input, and U-phase B-EMF connection pin for sensorless Actuator small signal GND Actuator small signal GND SPN driver power supply U-phase Hall –input, and center tap connection pin for sensorless V-phase Hall +input, and V-phase B-EMF connection pin for sensorless V-phase Hall –input, and center tap connection pin for sensorless
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HA13631T
Pin Description (cont)
Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Pin Name HW+ HW– VCTL REFIN RT CT1 CT2 PWMDC SGND VSS OP2IN TRKIN TRKN TRKP FCSGND VFCS FCSP FCSN FCSN OP1IN NC NC ASGND Function W-phase Hall +input, and W-phase B-EMF connection pin for sensorless W-phase Hall –input, and center tap connection pin for sensorless SPN driver control input Reference voltage for control inputs. Common to all drivers. Reference voltage. The IC’s internal reference current is determined by this voltage and the external resistor Rt. Time constant for clock oscillation. The oscillator frequency is determined by the external capacitor and resistor Ct1 and Rt. Time constant for PWM carrier. The amplitude is determined by the value of the external capacitor Ct1. Phase compensation connection pin for matching PWM carrier DC level with REFIN SPN small signal GND Control block power supply. 5 V Inverted input of OP amp. 2 for TRK driver control TRK driver control input TRK driver N output TRK driver P output FCS and TRK driver GND FCS driver power supply FCS driver P output FCS driver N output FCS driver control input Inverted input of OP amp. 1 for FCS driver control No connection No connection Actuator small signal GND
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HA13631T
Block Diagram
U V W CT VSS FGOUT EXTCOM VSPN
43 27 31 32 33 34 35
Zero cross detection
22
21
30
U Logic CLK 1.5 A V SPN output W
17 19 20
Rnf
26
COMM 23 VCTL 36 SPN FCS TRK SLD TRY PWM control Vref
18
C104 PWM carrier OTSD Vbst
BRKSEL 24 CE 25
ENABLE
41 40
Ct2
16
Bias
Rt
38 39
Ct1
CLK OSC
15 14 13
C103 BP2 C103 BP1
CLK
REFIN 37 + OP1IN 53 FCSIN 52 + OP2IN 44 TRKIN 45 − OP2 PWM control Vbst TRK N P − OP1 PWM control Vbst FCS N P
49 VFCS 50 51
47 46 48 5 VSLD
+ OP3IN 3 SLDIN 2 − OP3
PWM control
Vbst SLD
P N
7 8 54 55 10 VTRY
M
+ OP4IN 4 TRYIN 6 5k − OP4
PWM control
Vbst TRY
P N
11 12
M
42
SGND
1
28
29
56
9
5
HA13631T
Timing Chart
1. Start-up
EN H L H L
T2 T4 T1 T3 T5 T6 T7 T8 T9 Tmext T10
EXTCOM
COMM
H L Vspn
Output voltage (U phase) 0 Vspn Output voltage (V phase) 0 Vspn Output voltage (W phase) 0 + Output current (U phase) 0 − + Output current (V phase) 0 − + Output current (W phase) 0 − H L
PWM
PWM
PWM
PWM
PWM
FGOUT
Mute (B-EMF detection) Notes: 1. T1 to T10, and Tmext are set by CPU. 2. B-EMF sensing is masked while COMM = H. Also, when EXTCOM = H, B-EMF sensing is masked during the period from T1 to T6.
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