Document
Integrated Circuit Systems, Inc.
ICS9248-146
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application: Single chip clock solution for SIS630S chipsets. Output Features: • 3- CPUs @ 2.5V • 13 - SDRAM @ 3.3V • 6- PCI @3.3V, • 2 - AGP @ 3.3V • 1- 48MHz, @3.3V fixed. • 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz) • 2- REF @3.3V, 14.318MHz. Features: • Up to 166MHz frequency support • Support FS0-FS3 trapping status bit for I2C read back. • Support power management: CPU, PCI, SDRAM stops and Power down Mode form I2C programming. • Spread spectrum for EMI control (0 to -0.5%, ± 0.25%). • Uses external 14.318MHz crystal Skew Specifications: • CPU - CPU: < 175ps • SDRAM - SDRAM < 250ps (except SDRAM12) • PCI - PCI: < 500ps • CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDA *(AGPSEL)REF0 1 *(FS3)REF1 GND X1 X2 VDDPCI *(FS1)PCICLK_F *(FS2)PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 GND VDDAGP AGPCLK0 AGPCLK1 GND GND *(FS0)48MHz *(MODE)24_48MHz VDD48 SDATA SCLK
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDL CPUCLK0 CPUCLK1 CPUCLK2 GND VDDSDR SDRAM0 SDRAM1 SDRAM2 GND SDRAM3 SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 GND SDRAM8/PD# SDRAM9/SDRAM_STOP# GND SDRAM10/PCI_STOP# SDRAM11/CPU_STOP# SDRAM12 VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND. 1 These are double strength.
Block Diagram
Functionality
FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 66.67 100.00 166.67 133.33 66.67 100.00 100.00 133.33 112.00 124.00 138.00 150.00 66.67 100.00 150.00 160.00 SDRAM PCICLK 66.67 100.00 166.67 133.33 100.00 66.67 133.33 100.00 112.00 124.00 138.00 150.00 133.33 150.00 100.00 120.00 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.60 31.00 34.50 30.00 33.33 30.00 30.00 30.00 AGP SEL AGP SEL =0 =1 66.67 50.00 66.67 50.00 66.66 55.56 66.67 50.00 66.67 50.00 66.67 50.00 66.67 50.00 66.67 50.00 67.20 56.00 62.00 46.50 69.00 51.75 60.00 50.00 66.67 60.00 60.00 60.00 50.00 50.00 50.00 48.00
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum
48MHz 24_48MHz
2
REF(1:0)
CPU DIVDER
Stop
3
CPUCLK (2:0)
SDRAM DIVDER
Stop
13
SDRAM (12:0)
SDATA SCLK FS(3:0) PD# PCI_STOP# CPU_STOP# SDRAM_STOP# MODE AGP_SEL
Control Logic
PCI DIVDER
Stop
5
PCICLK (4:0) PCICLK_F
AGP DIVDER
Config. Reg.
2
AGP (1:0)
9248-146 RevA- 4/23/01 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-146
ICS9248-146
General Description
The ICS9248-146 is the single chip clock solution for Desktop/Notebook designs using the SIS 630S style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-146 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
Analog VDDA = X1, X2, Core, PLL VDD48 = 48MHz, 24MHz, fixed PLL Digital VDDPCI = PCICLK_F, PCICLK VDDSDR = SDRAM VDDAGP=AGP, REF MODE Pin Power Management Control Input
M ODE Pin 21 0 1 Pin 27 SDRAM11 CPU_STOP# Pin 28 SDRAM10 PCI_STOP# Pin 30 SDRAM9 SDRAM_STOP# Pin 31 SDRAM8 PD#
Pin Configuration
PIN N U MBER 1, 7, 15, 22, 25, 35, 43 2 3 4, 14, 18, 19, 29, 32, 39, 44 5 6 8 9 13, 12, 11, 10 17, 16, 20 PIN N A ME VDD A G P S EL REF0 F S3 REF1 GND X1 X2 F S1 PCICLK _F F S2 PCICLK 0 PCICLK (4:1) A G P (1:0) F S0 48M H z M ODE 24_48M H z 23 24 27 SD A TA S CLK CP U _S TO P # SD RA M 11 28 PCI_STO P # SD RA M 10 S D RA M 9 30 S D RA M _STO P # TY PE P WR IN OUT IN OUT P WR IN OUT IN OUT IN OUT OUT OUT IN OUT IN OUT I/O IN IN OUT IN OUT OUT IN D ES C R IPTION 3.3V P ow er supply for SD RA M output buffers, PCI output buffers, reference output buffers and 48M H z output A G P frequency select pin. 14.318 M H z reference clock. F requency select pin. 14.318 M H z reference clock. G round pin for 3V outputs. Crystal input,nominally 14.318M H z. Crystal output, nominally 14.318M H z. F requency select pin. P CI clock output, not affected by P CI_STO P # F requency select pin. P CI clock output. P CI clock outputs. A G P outputs defined as 2X PCI. These may not be stopped. F requency select pin. 48M H z output clock P in 27, 28, 30, & 31 function select pins 0=D esktop 1=M obile mode Clock output for super I/O /U S B default.