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M464S1724DTS Dataheets PDF



Part Number M464S1724DTS
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 16Mx64 SDRAM SODIMM based on 8Mx16 / 4Banks /4K Refresh / 3.3V Synchronous DRAMs with SPD
Datasheet M464S1724DTS DatasheetM464S1724DTS Datasheet (PDF)

M464S1724DTS M464S1724DTS SDRAM SODIMM PC133/PC100 SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M464S1724DTS is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S1724DTS consists of eight CMOS 8M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on .

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M464S1724DTS M464S1724DTS SDRAM SODIMM PC133/PC100 SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M464S1724DTS is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S1724DTS consists of eight CMOS 8M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S1724DTS is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. • • • • • FEATURE • Performance range Part No. M464S1724DTS-L7C/C7C M464S1724DTS-L7A/C7A M464S1724DTS-L1H/C1H M464S1724DTS-L1L/C1L Max Freq. (Speed) 133MHz (7.5ns @ CL=2) 133MHz (7.5ns @ CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,250mil) , double sided component PIN CONFIGURATIONS (Front side/back side) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front V SS DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 V SS DQM0 DQM1 V DD A0 A1 A2 V SS DQ8 DQ9 DQ10 DQ11 V DD DQ12 DQ13 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back V SS DQ32 DQ33 DQ34 DQ35 V DD DQ36 DQ37 DQ38 DQ39 V SS DQM4 DQM5 V DD A3 A4 A5 V SS DQ40 DQ41 DQ42 DQ43 V DD DQ44 DQ45 Pin 51 53 55 57 59 Front DQ14 DQ15 V SS NC NC Pin 52 54 56 58 60 Back DQ46 DQ47 V SS NC NC Pin Front DQ21 DQ22 DQ23 V DD A6 A8 V SS A9 A10/AP V DD DQM2 DQM3 V SS DQ24 DQ25 DQ26 DQ27 V DD DQ28 DQ29 DQ30 DQ31 V SS **SDA V DD Pin Back 95 97 99 101 103 105 107 Voltage Key 109 CLK0 62 CKE0 111 V DD 64 V DD 113 RAS 66 CAS 115 WE 68 CKE1 117 CS0 70 *A12 119 CS1 72 *A13 121 DU 74 CLK1 123 V SS 76 V SS 125 NC 78 NC 127 NC 80 NC 129 V DD 82 V DD 131 DQ16 84 DQ48 133 DQ17 86 DQ49 135 DQ18 88 DQ50 137 DQ19 90 DQ51 139 V SS 92 V SS 141 DQ20 94 DQ52 143 96 DQ53 98 DQ54 100 DQ55 102 V DD 104 A7 106 BA0 108 V SS 110 BA1 112 A11 114 V DD 116 DQM6 118 DQM7 120 V SS 122 DQ56 124 DQ57 126 DQ58 128 DQ59 130 V DD 132 DQ60 134 DQ61 136 DQ62 138 DQ63 140 V SS 142 **SCL 144 V DD PIN NAMES Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK1 CKE0 ~ CKE1 CS0 ~ CS1 RAS CAS WE DQM0 ~ 7 V DD V SS SDA SCL DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Serial data I/O Serial clock Don ′t use No connection 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.1 Sept. 2001 M464S1724DTS PIN CONFIGURATION DESCRIPTION Pin CLK CS Name System clock Chip select PC133/PC100 SODIMM Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+t SS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. CKE Clock enable A0 ~ A11 Address BA0 ~ BA1 RAS Bank select address Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 D Q0 ~ 63 Data input/output mask Data input/output.


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