MBM29DL32xBD

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20873-4E FLASH MEMORY CMOS 32M (4M × 8/2M × 16) BIT Dual Operation MBM29DL32XTD/BD s FEATURES -80/90/12 0.33 µm Process Technology Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to Table 1) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program Single 3.0 V read, program, and erase Minimizes system level power requirements (Continued) s PRODUCT LINE UP Part No. VCC = 3.3 V Ordering Part No. VCC = 3.0 V Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) +0.3 V –0.3 V +0.6 V –0.3 V MBM29DL32XTD/MBM29DL32XBD 80 — 80 80 30 — 90 90 90 35 — 12 120 120 50 s PACKAGES 48-pin plastic TSOP (I) Marking Side 48-pin plastic TSOP (I) 57-ball plastic FBGA Marking Side (FPT-48P-M19) (FPT-48P-M20) (BGA-57P-M01) Em\edded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. MBM29DL32XTD/BD-80/90/12 (Continued) Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 57-ball FBGA (Package suffix: PBT) Minimum 100,000 program/erase cycles High performance 80 ns maximum access time Sector erase architecture Eight 4K word and sixt...