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MBM29F002BC Dataheets PDF



Part Number MBM29F002BC
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description 2M (256K X 8) BIT
Datasheet MBM29F002BC DatasheetMBM29F002BC Datasheet (PDF)

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20868-3E FLASH MEMORY CMOS 2M (256K × 8) BIT MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90 s FEATURES • • Single 5.0 V read, write, and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection 32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix: PD) Minimum 100,000 write/e.

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FUJITSU SEMICONDUCTOR DATA SHEET DS05-20868-3E FLASH MEMORY CMOS 2M (256K × 8) BIT MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90 s FEATURES • • Single 5.0 V read, write, and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection 32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix: PD) Minimum 100,000 write/erase cycles High performance 55 ns maximum access time Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes Any combination of sectors can be erased. Also supports full chip erase Boot Code Sector Architecture T = Top sector B = Bottom sector Embedded Erase™ Algorithms Automatically pre-programs and erases the chip or any sector Embedded Program™ Algorithms Automatically programs and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Low VCC write inhibit ≤ 3.2 V Hardware RESET pin Resets internal state machine to the read mode Erase Suspend/Resume Supports reading or programming data to a sector not being erased Sector protection Hardware method that disables any combination of sector from write or erase operation Temporary sector unprotection Temporary sector unprotection via the RESET pin • • • • • • • • • • • • • Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc. MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90 s PACKAGE 32-pin plastic TSOP(I) Marking Side 32-pin plastic TSOP(I) Marking Side (FPT-32P-M24) (FPT-32P-M25) 32-pin plastic QFJ (PLCC) Marking Side (LCC-32P-M02) 2 MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90 s GENERAL DESCRIPTION The MBM29F002TC/BC is a 2 M-bit, 5.0 V-Only Flash memory organized as 256K bytes of 8 bits each. The MBM29F002TC/BC is offered in a 32-pin TSOP(I) and 32-pin PLCC packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29F002TC/BC offers access times between 55 ns and 90 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29F002TC/BC is command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices. The MBM29F002TC/BC is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within 1 second (if already completely preprogrammed). The MBM29F002TC/BC is erased when shipped from the factory. The MBM29F002TC/BC device also features hardware sector protection. This feature will disable both program and erase operations in any number of secotrs (0 through 6). Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved. The device features single 5.0 V power supply operation for both read and program functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of DQ7, or by the Toggle Bit I feature on DQ6. Once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. The MBM29F002TC/BC also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program or Embedded Erase operations will be terminated. The internal state machi.


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