MN3890S

CCD Delay Line Series MN3890S NTSC-Compatible CCD 1 H Video Signal Delay Element Overview The MN3890S is a 1 H image delay element of a 4 fSC CMOS CCD and suitable for video signal processing applications. It contains such components as a frequency-doubler circuit, a shift register clock driver, a 906-stage CCD analog shift register, and a resampling output amplifier. The MN3885S drives and samples the 906-stage analog shift register using a redoubled version of the supplied clock signal with a frequency 7.16 MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces a delay of 1 H (the horizontal scan period). Pin Assignment VIN VBB VDD VSS 1 2 3 4 8 7 6 5 VO VGC PCOUT & VCOIN XI ( TOP VIEW ) SOP008-P-0225A Features Single 5.0 V power supply Energy-saving design based on CMOS process Low EMI levels from clock during driving Applications VCRs, Video cameras Structure and Operation The MN3890S consists of the operational blocks shown in the block diagram. Frequency-doubler circuit When the 7.16 MHz of the doubled NTSC color signal subcarrier frequency is inputted from the clock input pin XI, 14.32 MHz clock of fourfold frequency of color signal subcarrier is generated by this circuit. Clock driver This block generates two transfer clock signals, ø1 and ø2, synchronized with the 14.32 MHz clock signal from the frequency-doubler circuit. It also generates the sampling clock signals øS and øS', resampling clock signa...