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STP7NC80Z Dataheets PDF



Part Number STP7NC80Z
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description N-CHANNEL MOSFET
Datasheet STP7NC80Z DatasheetSTP7NC80Z Datasheet (PDF)

STP7NC80Z - STP7NC80ZFP STB7NC80Z - STB7NC80Z-1 N-CHANNEL 800V - 1.3Ω - 6.5A TO-220/FP/D2PAK/I2PAK Zener-Protected PowerMESH™III MOSFET TYPE STP7NC80Z STP7NC80ZFP STB7NC80Z STB7NC80Z-1 s s VDSS 800 800 800 800 V V V V RDS(on) < < < < 1.5 Ω 1.5 Ω 1.5 Ω 1.5 Ω ID 6.5 A 6.5 A 6.5 A 6.5 A TO-220 3 1 s s s TYPICAL RDS(on) = 1.3Ω EXTREMELY HIGH dv/dt AND CAPABILITY GATE TO - SOURCE ZENER DIODES 100% AVALANCHE TESTED VERY LOW GATE INPUT RESISTANCE GATE CHARGE MINIMIZED D2PAK 3 1 2 TO-220FP 12 .

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STP7NC80Z - STP7NC80ZFP STB7NC80Z - STB7NC80Z-1 N-CHANNEL 800V - 1.3Ω - 6.5A TO-220/FP/D2PAK/I2PAK Zener-Protected PowerMESH™III MOSFET TYPE STP7NC80Z STP7NC80ZFP STB7NC80Z STB7NC80Z-1 s s VDSS 800 800 800 800 V V V V RDS(on) < < < < 1.5 Ω 1.5 Ω 1.5 Ω 1.5 Ω ID 6.5 A 6.5 A 6.5 A 6.5 A TO-220 3 1 s s s TYPICAL RDS(on) = 1.3Ω EXTREMELY HIGH dv/dt AND CAPABILITY GATE TO - SOURCE ZENER DIODES 100% AVALANCHE TESTED VERY LOW GATE INPUT RESISTANCE GATE CHARGE MINIMIZED D2PAK 3 1 2 TO-220FP 12 3 I2PAK (Tabless TO-220) DESCRIPTION The third generation of MESH OVERLAY™ Power MOSFETs for very high voltage exhibits unsurpassed on-resistance per unit area while integrating back-to-back Zener diodes between gate and source. Such arrangement gives extra ESD capability with higher ruggedness performance as requested by a large variety of single-switch applications. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS SINGLE-ENDED SMPS IN MONITORS, COMPUTER AND INDUSTRIAL APPLICATION s WELDING EQUIPMENT s ORDERING INFORMATION SALES TYPE STP7NC80Z STP7NC80ZFP STB7NC80ZT4 STB7NC80Z-1 MARKING P7NC80Z P7NC80ZFP B7NC80Z B7NC80Z PACKAGE TO-220 TO-220FP D2PAK I2PAK PACKAGING TUBE TUBE TAPE & REEL TUBE May 2003 1/13 STP7NC80Z - STP7NC80ZFP - STB7NC80Z - STB7NC80Z-1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter STP7NC80Z STB7NC80Z STB7NC80Z-1 VDS VDGR VGS ID ID IDM ( ) PTOT IGS VESD(G-S) dv/dt VISO Tstg Tj Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Gate-source Current Gate source ESD(HBM-C=100pF, R=1.5KΩ) Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max.Operating Junction Temperature --65 to 150 150 6.5 4 26 135 1.08 ±50 3 3 2000 800 800 ±25 6.5 (*) 4(*) 26 (*) 40 0.32 Value STP7NC80ZFP V V V A A A W W/°C mA KV V/ns V °C °C Unit ( ) Pulse width limited by safe operating area (*) Limited only by maximum temperature allowed THERMAL DATA TO-220 / D2PAK / I2PAK Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.93 30 300 TO-220FP 3.13 °C/W °C/W °C AVALANCHE CHARACTERISTICS Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value 6.5 290 Unit A mJ GATE-SOURCE ZENER DIODE Symbol BVGSO αT Rz Parameter Gate-Source Breakdown Voltage Voltage Thermal Coefficient Dynamic Resistance Test Conditions Igs=± 1mA (Open Drain) T=25°C Note(3) ID = 20 mA, Min. 25 1.3 90 Typ. Max. Unit V 10-4/°C Ω PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/13 STP7NC80Z - STP7NC80ZFP - STB7NC80Z - STB7NC80Z-1 ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol V(BR)DSS Parameter Drain-source Breakdown Voltage Test Conditions ID = 250 µA, VGS = 0 ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ± 20V VDS = VGS, ID = 250µA VGS = 10V, ID = 3.3 A 3 4 1.3 Min. 800 0.9 1 50 ±10 5 1.5 Typ. Max. Unit V V/°C µA µA µA V Ω ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient IDSS IGSS VGS(th) RDS(on) Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS > ID(on) x RDS(on)max, ID = 3.3 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 6 2350 164 17 Max. Unit S pF pF pF SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Test Conditions VDD = 400 V, ID = 3 A RG = 4.7Ω VGS = 10 V ( see test circuit, Figure 3) VDD = 640 V, ID = 6 A, VGS = 10V Min. Typ. 33 12 43 12 15 58 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 640 V, ID =6 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Min. Typ. 13 13 20 Max. Unit ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD =6.1 A, VGS = 0 ISD = 6 A, di/dt = 100A/µs VDD = 40V, Tj = 150°C (see test circuit, Figure .


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