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SPT7721 Dataheets PDF



Part Number SPT7721
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description 8-BIT / 250 MSPS ADC WITH DEMUXED OUTPUTS
Datasheet SPT7721 DatasheetSPT7721 Datasheet (PDF)

SPT7721 8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS TECHNICAL DATA NOVEMBER 8, 2001 FEATURES • • • • • • TTL/CMOS/PECL compatible High conversion rate: 250 MSPS Single +5 V power supply Very low power dissipation: 310 mW Power-down mode +3.0 V/+5.0 V (LVCMOS) digital output logic compatibility • Demuxed output ports APPLICATIONS • • • • RGB video processing Digital communications High-speed instrumentation Projection display systems GENERAL DESCRIPTION The SPT7721 is a high-speed, 8-bit analog-t.

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SPT7721 8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS TECHNICAL DATA NOVEMBER 8, 2001 FEATURES • • • • • • TTL/CMOS/PECL compatible High conversion rate: 250 MSPS Single +5 V power supply Very low power dissipation: 310 mW Power-down mode +3.0 V/+5.0 V (LVCMOS) digital output logic compatibility • Demuxed output ports APPLICATIONS • • • • RGB video processing Digital communications High-speed instrumentation Projection display systems GENERAL DESCRIPTION The SPT7721 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 310 mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5 V common mode reference is provided on chip for the singleended input mode to minimize external components. The SPT7721 digital outputs are demuxed (double-wide) with both dual-channel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0 V and +5.0 V compatible. The SPT7721 is available in a 44-lead TQFP surface mount package over the industrial temperature range of –40 to +85 °C. BLOCK DIAGRAM AGND DGND AVCC OVDD VIN+ VIN– 8-Bit 250 MSPS ADC CLK CLK Data Output Latches DA0–DA7 DB0–DB7 Common Mode Voltage Reference Data Output Mode Control 2 2 DCLKOUT DCLKOUT +2.5 V VCM PD CLK CLK Reset DMODE1,2 & Reset ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C Supply Voltages AVCC ...................................................................... +6 V OVDD ..................................................................... +6 V Input Voltages Analog Inputs ............................... –0.5 V to VCC +0.5 V Digital Inputs ................................ –0.5 V to VCC +0.5 V Temperatures Operating Temperature ........................... –40 to +85 °C Storage Temperature ............................ –65 to +125 °C Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, AVCC = +5.0 V, ƒCLK = 250 MHz, VCM = 2.5 V, OVDD = 5.0 V, unless otherwise specified. PARAMETERS Resolution DC Performance Differential Linearity Error (DLE) Integral Linearity Error (ILE) Best Fit No Missing Codes Analog Input Input Voltage Range (with respect to VIN–) Gain Variation Input Common Mode (VCM) Input Bias Current Input Resistance Input Capacitance Input Bandwidth Offset Error Offset Power Supply Rejection Ratio Timing Characteristics Maximum Conversion Rate Output Delay (Clock-to-Data) (tpd1) Output Delay Tempco Aperture Delay Time (tap) Aperture Jitter Time Pipeline Delay (Latency) Single Channel Mode Demuxed Interleaved Mode Demuxed Parallel Mode Channel B Channel A CLK to DCLKOUT Delay Time Single Channel Mode (tpd2) Dual Channel Mode (tpd3) Dynamic Performance Effective Number of Bits (ENOB) ƒIN = 70 MHz ƒIN = 70 MHz Signal-to-Noise Ratio (SNR) ƒIN = 70 MHz ƒIN = 70 MHz TEST CONDITIONS TEST LEVEL MIN SPT7721 TYP 8 MAX UNITS Bits LSB LSB LSB LSB ƒIN = 1 kHz +25 °C –40 °C to +85 °C +25 °C –40 °C to +85 °C +25 °C, ƒIN = 1 kHz V V V V I –0.70/+1.05 –0.95/+1.5 ±1.7 ±2.25 Guaranteed +25 °C +25 °C +25 °C +25 °C (–3 dB of FS) V VI IV VI V V V VI V VI IV V IV IV V V V V IV IV 2.3 ±470 2 2.5 10 50 4 220 ±10 0.5 3.0 mVP-P % V µA kΩ pF MHz mV mV/V MSPS ns ps/°C ns ps rms Clocks Clocks Clocks Clocks –40 °C to +85 °C 250 6 8 22 0.5 2 2.5 2.5 2.5 3.5 10.5 4 5.3 6 6.16 7 7.8 ns ns +25 °C –40 °C to +85 °C +25 °C –40 °C to +85 °C VI IV VI IV 5.8 5.5 42 36 6.4 6.0 43 40 Bits Bits dB dB SPT7721 2 11/8/01 ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, AVCC = +5.0 V, ƒCLK = 250 MHz, VCM = 2.5 V, OVDD = 5 V, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL MIN SPT7721 TYP MAX UNITS Dynamic Performance Total Harmonic Distortion (THD) +25 °C ƒIN = 70 MHz –40 °C to +85 °C ƒIN = 70 MHz Signal-to-Noise and Distortion (SINAD) +25 °C ƒIN = 70 MHz –40 °C to +85 °C ƒIN = 70 MHz Power Supply Requirements AVCC Voltage (Analog Supply) OVDD Voltage (Digital Supply) AVCC Current Power Dissipation with Internal Voltage Reference Common Mode Reference Voltage Voltage Tempco Output Impedance Power Supply Rejection Ratio VI IV VI IV IV IV VI VI VI V V V VI IV IV IV IV IV VI VI IV IV VI VI VI VI V V V V 37 35 4.75 2.75 –43 –42 40 38 5.0 62 310 2.45 2.5 100 1 63 –40 –37 dB dB dB dB 5.25 5.25 70 350 2.55 V V mA mW V ppm/°C kΩ mV/V mVP-P V V V V V µA µA V V µA µA V V ns ns ns ns IOUT = ±50 µA Clock and Reset Inputs (Differential and Single-Ended) Differential Signal Amplitude (VDIFF) Differential High Input Voltage (VIHD) Differential Low Input Voltage (VILD) Differential Common-Mode Input (VCMD) Single-Ended High Input Voltage (VIH) Single-Ended Low Input Voltage (VIL) VID = .


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