Document
L6710
6 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT
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2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD TRANSIENT RESPONSE INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT 6 BIT PROGRAMMABLE OUTPUT COMPLIANT WITH VRD 10 DYNAMIC VID MANAGEMENT 0.5% OUTPUT VOLTAGE ACCURACY 10% ACTIVE CURRENT SHARING ACCURACY DIGITAL 2048 STEP SOFT-START OVERVOLTAGE PROTECTION OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S RdsON OR A SENSE RESISTOR OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 150kHz POWER GOOD OUTPUT AND ENABLE FUNCTION INTEGRATED REMOTE SENSE BUFFER
TQFP44 (10 x 10 x 1mm) Exposed Pad ORDERING NUMBERS:L6710 L6710TR (Tape & Reel)
APPLICATIONS ■ POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS ■ POWER SUPPLY FOR SERVER AND WORKSTATION ■ DISTRIBUTED POWER SUPPLY PIN CONNECTION (top view)
DESCRIPTION The device implements a two phase step-down controller with a 180 phase-shift between each phase with integrated high current drivers in a compact 10x10mm body package with exposed pad. A precise 6-bit digital to analog converter (DAC) allows adjusting the output voltage from 0.8375V to 1.6000V with 12.5mV binary steps managing Dynamic VID code changes. The high precision internal reference assures the selected output voltage to be within 0.5% over line and temperature variations. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current, the system works in Constant Current mode until UVP
N.C. HGATE2 PHASE2 N.C. LGATE2 PGND LGATE1 VCCDR PHASE1 HGATE1 N.C.
33 32 31 30 29 28 27 26 25 24 23 22 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 21 20 19 18 17 16 15 14 13 12 10 11
N.C. N.C. BOOT2 PGOOD VID5 VID4 VID3 VID2 VID1 VID0 N.C. OSC / FAULT ISEN2 PGNDS ISEN1 FBG FBR N.C. N.C. OUTEN VSEN REF_OUT
March 2004
N.C. N.C. BOOT1 N.C. VCC SGND SGND COMP FB N.C. N.C.
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L6710
BLOCK DIAGRAM
OSC / FAULT SGND VCCDR BOOT1 2 PHASE OSCILLATOR OUTEN PGOOD
LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION
HS
U GATE1
PWM1
PHASE1
DIGITAL SOFT-START
CURRENT CORRECTION
LOGIC AND PROTECTIONS
CH1 OCP
LS
LGATE1 ISEN1
VCC VCCDR TO TAL CURRENT CURRENT AVG
VID5 VID4 VID3 VID2 VID1 VID0 VSEN
CURRENT READING
DAC
PGND
CURRENT READING
CURRENT CORRECTION
PGNDS ISEN2
CH2 OCP CH1 OCP
32k
CH2 OCP
FBG FBR
32k 32k
I FB
LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION
LS
LGATE2
PHASE2 HS UGATE2 BOOT2
PWM2
32k
REMOTE BUFFER
ERROR AMPL IFIER
Vcc
REF_OUT
FB
COMP
Vcc
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc, VCCDR VBOOT-VPHASE VUGATE1-VPHASE1 VUGATE2-VPHASE2 LGATE1, PHASE1, LGATE2, PHASE2 to PGND VID0 to VID5 All other pins to PGND VPHASEx Sustainable Peak Voltage. T<20nS @ 600kHz To PGND Boot Voltage Parameter Value 15 15 15 -0.3 to Vcc+0.3 -0.3 to 5 -0.3 to 7 26 Unit V V V V V V V
THERMAL DATA
Symbol Rth j-amb Tmax Tstg Tj PMAX Parameter Thermal Resistance Junction to Ambient Maximum junction temperature Storage temperature range Junction Temperature Range Max power dissipation at Tamb=25°C Value 40 150 -40 to 150 0 to 125 2.5 Unit °C/W °C °C °C W
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L6710
PIN FUNCTION
N 1 2 3 Name N.C. N.C. BOOT1 Not internally bonded. Not internally bonded. Channel 1 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode to VCC (cathode vs. boot). Not internally bonded. Device supply voltage. The operative supply voltage is 12V ±15%. Filter with 1µF (Typ.) capacitor vs. GND. All the internal references are referred to this pin. Connect it to the PCB signal ground. This pin is connected to the error amplifier output and is used to compensate the control feedback loop. This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. A current proportional to the sum of the current sensed in both channel is sourced from this pin (50µA at full load, 70µA at the Constant Current threshold). Connecting a resistor between this pin and VSEN pin allows programming the droop effect. Not internally bonded. Reference voltage output used for voltage regulation. The pin is protected against short circuit vs. ground. Filter to SGND with 47nF ceramic capacitor. Manages Over&Under-voltage conditions and the PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote Sense of the regulated voltage. If no Remote Sense is implemented, connect it directly to the regulated voltage in order to manage OVP, UVP and PGOOD. Connecting 1nF capacitor max vs. SGND can help in reducing noise injection. Output Enable pin. Internally 3V pulled-up. If forced to a voltage lower than 0.4V, the device stops operation with all mosf.