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M470T6554CZ0 Dataheets PDF



Part Number M470T6554CZ0
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description DDR2 Unbuffered SODIMM
Datasheet M470T6554CZ0 DatasheetM470T6554CZ0 Datasheet (PDF)

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC Revision 1.1 March 2005 Rev. 1.1 Mar. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 Unbuffered SODIMM Ordering Information Part Number M470T3354CZ0-C(L)D6/E6/D5/CC M470T6554CZ0-C(L)D6/E6/D5/CC M470T2953CZ0-C(L)D6/E6/D5/CC DDR2 SDRAM Number of Rank 1 2 2 Density 256MB 512MB 1GB Organization 32Mx64 64Mx64 128Mx64 Component Composition 32Mx16(K4T51163QC-C(L)D6.

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256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC Revision 1.1 March 2005 Rev. 1.1 Mar. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 Unbuffered SODIMM Ordering Information Part Number M470T3354CZ0-C(L)D6/E6/D5/CC M470T6554CZ0-C(L)D6/E6/D5/CC M470T2953CZ0-C(L)D6/E6/D5/CC DDR2 SDRAM Number of Rank 1 2 2 Density 256MB 512MB 1GB Organization 32Mx64 64Mx64 128Mx64 Component Composition 32Mx16(K4T51163QC-C(L)D6/E6/D5/CC)*4 32Mx16(K4T51163QC-C(L)D6/E6/D5/CC)*8 64Mx8(K4T51083QC-C(L)D6/E6/D5/CC)*16 Height 30mm 30mm 30mm Note: “Z” of Part number stand for Lead-free products. Features • Performance range D6(DDR2-667) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 667 667 4-4-4 E6(DDR2-667) 400 533 667 5-5-5 D5(DDR2-533) 400 533 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin • 4 independent internal banks • Posted CAS • Programmable CAS Latency: 3, 4, 5 • Programmable Additive Latency: 0, 1 , 2 , 3 and 4 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination with selectable values(50/75/150 ohms or disable) • PASR(Partial Array Self Refresh) • Average Refesh Period 7.8us at lower a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh rate enable feature • Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA 32Mx16 - RoHS Compliant Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. Address Configuration Organization 64Mx8(512Mb) based Module 32Mx16(512Mb) based Module Row Address A0-A13 A0-A12 Column Address A0-A9 A0-A9 Bank Address BA0-BA1 BA0-BA1 Auto Precharge A10 A10 Rev. 1.1 Mar. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs Pin Configurations (Front side/Back side) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 DDR2 SDRAM Back A0 VDD BA1 RAS S0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS Front VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0 VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC Pin 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Front DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 Pin 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Back DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC NC VDD A11 A7 A6 VDD A4 A2 Pin 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Front A1 VDD A10/AP BA0 WE VDD CAS NC/S1 VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS Pin 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Pin 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front DQ42 DQ43 VSS DQ48 DQ49 VSS NC, TEST VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD Pin 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1 Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Pin Description Pin Name CK0,CK1 CK0,CK1 CKE0,CKE1 RAS CAS WE S0,S1 A0~A9, A11~A13 A10/AP BA0,BA1 ODT0,ODT1 SCL Function Clock Inputs, positive line Clock Inputs, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address On-die termination control Serial Presence Detect(SPD) Clock Input Pin Name SDA SA1,SA0 DQ0~DQ63 DM0~DM7 DQS0~DQS7 DQS0~DQS7 TEST VDD VSS VREF VDDSPD NC SPD address Data Input/Output Data Masks Data strobes Function SPD Data Input/Output Data strobes complement Logic Analyzer specific test pin (No connect on So-DIMM) Core and I/O Power Ground Input/Output Reference SPD Power Spare pins, No connect Rev. 1.1 Mar. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs Input/Output Functional Description Symbol CK0-CK1 CK0-CK1 Type Input Function DDR2 SDRAM The system clock inputs. All address and command lines are sam.


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