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A54SXxxA Dataheets PDF



Part Number A54SXxxA
Manufacturers Actel
Logo Actel
Description SX-A Family FPGAs
Datasheet A54SXxxA DatasheetA54SXxxA Datasheet (PDF)

v5.1 SX-A Family FPGAs Leading-Edge Performance • • 250 MHz System Performance 350 MHz Internal Performance • • • • • • • • • • ™ Specifications • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops 0.22 µ / 0.25 µ CMOS Process Technology Features • • • • Hot-Swap Compliant I/Os Power-Up/Down Friendly (No Sequencing Required for Supply Voltages) 66 MHz PCI Compliant Nonvolatile, Single-Chip Solution Configurable I/O Support fo.

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v5.1 SX-A Family FPGAs Leading-Edge Performance • • 250 MHz System Performance 350 MHz Internal Performance • • • • • • • • • • ™ Specifications • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops 0.22 µ / 0.25 µ CMOS Process Technology Features • • • • Hot-Swap Compliant I/Os Power-Up/Down Friendly (No Sequencing Required for Supply Voltages) 66 MHz PCI Compliant Nonvolatile, Single-Chip Solution Configurable I/O Support for 3.3 V / 5 V PCI, 5 V TTL, 3.3 V LVTTL, 2.5 V LVCMOS2 2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with 5 V Input Tolerance and 5 V Drive Strength Devices Support Multiple Temperature Grades Configurable Weak-Resistor Pull-Up or Pull-Down for I/O at Power-Up Individual Output Slew Rate Control Up to 100% Resource Utilization and 100% Pin Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Boundary-Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Actel Secure Programming Technology with FuseLock™ Prevents Reverse Engineering and Design Theft Table 1 • SX-A Product Profile Device Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks Boundary Scan Testing 3.3 V / 5 V PCI Input Set-Up (External) Speed Grades Temperature Grades Package (by pin count) PQFP TQFP PBGA FBGA CQFP A54SX08A 8,000 12,000 768 512 256 512* 130 3 0 Yes Yes 0 ns –F, Std, –1, –2 C, I, A, M 208 100, 144 – 144 – A54SX16A 16,000 24,000 1,452 924 528 990 180 3 0 Yes Yes 0 ns –F, Std, –1, –2, –3 C, I, A, M 208 100, 144 – 144, 256 – A54SX32A 32,000 48,000 2,880 1,800 1,080 1,980 249 3 0 Yes Yes 0 ns –F, Std, –1, –2, –3 C, I, A, M 208 100, 144, 176 329 144, 256, 484 208, 256 A54SX72A 72,000 108,000 6,036 4,024 2,012 4,024 360 3 4 Yes Yes 0 ns –F, Std, –1, –2, –3 C, I, A, M 208 – – 256, 484 208, 256 Note: *A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers February 2005 © 2005 Actel Corporation i See the Actel website for the latest version of the datasheet. SX-A Family FPGAs Ordering Information A54SX16A 2 PQ 208 Application (Temperature Range) Blank = Commercial (0 to +70˚) I = Industrial (-40 to +85˚C) A = Automotive (-40 to +125˚C) M = Military (-55 to +125˚C) B = MIL-STD-883 Class B Package Lead Count Package Type BG = 1.27 mm Plastic Ball Grid Array FG = 1.0 mm Fine Pitch Ball Grid Array PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack CQ = Ceramic Quad Flat Pack* Speed Grade Blank = Standard Speed –1 = Approximately 15% Faster than Standard –2 = Approximately 25% Faster than Standard –3 = Approximately 35% Faster than Standard –F = Approximately 40% Slower than Standard Part Number A54SX08A = 12,000 System Gates A54SX16A = 24,000 System Gates A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates Note: *For more information about the CQFP package options, refer to the HiRel SX-A datasheet. Device Resources User I/Os (Including Clock Buffers) Device A54SX08A A54SX16A A54SX32A A54SX72A 208-Pin PQFP 130 175 174 171 100-Pin TQFP 81 81 81 – 144-Pin TQFP 113 113 113 – 176-Pin TQFP – – 147 – 329-Pin PBGA – – 249 – 144-Pin FBGA 111 111 111 – 256-Pin FBGA – 180 203 203 484-Pin FBGA – – 249 360 Notes: Package Definitions: PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array ii v5.1 SX-A Family FPGAs Temperature Grade Offering Package PQ208 TQ100 TQ144 TQ176 BG329 FG144 FG256 FG484 CQ208 CQ256 Notes: 1. 2. 3. 4. 5. 6. 7. C = Commercial I = Industrial A = Automotive M = Military B = Mil-Std-883 Class B For more information regarding automotive products, refer to the SX-A Automotive Family FPGAs datasheet. For more information regarding Mil-Temp and ceramic packages, refer to the HiRel SX-A Family FPGAs datasheet. C,I,A,M C,I,A,M C,I,A,M A54SX08A C,I,A,M C,I,A,M C,I,A,M A54SX16A C,I,A,M C,I,A,M C,I,A,M A54SX32A C,I,A,M C,I,A,M C,I,A,M C,I,M C,I,M C,I,A,M C,I,A,M C,I,M C,M,B C,M,B C,I,A,M C,I,A,M C,M,B C,M,B A54SX72A C,I,A,M Speed Grade and Temperature Grade Matrix F Commercial Industrial Automotive Military Mil-Std. 883B Notes: 1. For more information regarding automotive products, refer to the SX-A Automotive Family FPGAs datasheet. 2. For more information regarding Mil-Temp and ceramic packages, refer to the HiRel SX-A Family FPGAs datasheet. ✓ Std ✓ ✓ ✓ ✓ ✓ ✓ ✓ –1 ✓ ✓ –2 ✓ ✓ –3 ✓ ✓ Contact your Actel Sales representative for more information on availability. v5.1 iii SX-A Family FPGAs Table of Contents General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Other Architectural Features . . . . . . . .


54SXxx A54SXxxA 54SXxxA


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