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STP85NF55L Dataheets PDF



Part Number STP85NF55L
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description N-CHANNEL POWER MOSFET
Datasheet STP85NF55L DatasheetSTP85NF55L Datasheet (PDF)

N-CHANNEL 55V - 0.0060 Ω - 80A D2PAK/TO-220 STripFET™ II POWER MOSFET TYPE STP85NF55L STB85NF55L s s s STB85NF55L STP85NF55L VDSS 55 V 55 V RDS(on) <0.008 Ω <0.008 Ω ID 80 A 80 A TYPICAL RDS(on) = 0.0060 Ω LOW THRESHOLD DRIVE LOGIC LEVEL DEVICE 3 1 3 1 2 DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteri.

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N-CHANNEL 55V - 0.0060 Ω - 80A D2PAK/TO-220 STripFET™ II POWER MOSFET TYPE STP85NF55L STB85NF55L s s s STB85NF55L STP85NF55L VDSS 55 V 55 V RDS(on) <0.008 Ω <0.008 Ω ID 80 A 80 A TYPICAL RDS(on) = 0.0060 Ω LOW THRESHOLD DRIVE LOGIC LEVEL DEVICE 3 1 3 1 2 DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s SOLENOID AND RELAY DRIVERS s MOTOR CONTROL, AUDIO AMPLIFIERS s DC-DC CONVERTERS s AUTOMOTIVE ENVIRONMENT Ordering Information SALES TYPE STP85NF55L STB85NF55L STB85NF55LT4 MARKING P85NF55L B85NF55L B85NF55L D2PAK TO-263 (Suffix “T4”) TO-220 ADD SUFFIX “T4” FOR ORDERING IN TAPE & REEL INTERNAL SCHEMATIC DIAGRAM PACKAGE TO-220 D2PAK D2PAK PACKAGING TUBE TUBE TAPE & REEL ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID(•) ID IDM (••) Ptot dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 55 55 ± 15 80 80 320 300 2.0 10 980 -55 to 175 Unit V V V A A A W W/°C V/ns mJ °C (•) Current Limited by Package. (••) Pulse width limited by safe operating area. September 2002 1) ISD ≤80A, di/dt ≤300A/µs, VDD ≤ V (BR)DSS, Tj ≤ TJMAX (2) Starting T j = 25 oC, ID = 40A, VDD = 30V 1/10 STB85NF55L STP85NF55L THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 0.5 62.5 300 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125°C VGS = ± 15 V Min. 55 1 10 ±100 Typ. Max. Unit V µA µA nA ON (*) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 5 V ID = 250 µA ID = 40 A ID = 40 A Min. 1 Typ. 1.6 0.0060 0.008 Max. 2.5 0.008 0.01 Unit V Ω Ω DYNAMIC Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15V ID = 40 A Min. Typ. 130 4050 860 300 Max. Unit S pF pF pF VDS = 25V f = 1 MHz VGS = 0 2/10 STB85NF55L STP85NF55L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 40 A VDD = 27.5 V VGS = 5 V RG = 4.7 Ω (Resistive Load, Figure 3) VDD=27.5V ID=80A VGS=5V (see test circuit, Figure 4) Min. Typ. 35 165 80 20 45 110 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 40 A VDD = 27.5 V VGS = 5 V RG = 4.7Ω, (Resistive Load, Figure 3) Min. Typ. 70 55 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (•) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80 A VGS = 0 80 240 6 Test Conditions Min. Typ. Max. 80 320 1.5 Unit A A V ns nC A ISD = 80 A di/dt = 100A/µs Tj = 150°C VDD = 20 V (see test circuit, Figure 5) (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/10 STB85NF55L STP85NF55L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/10 STB85NF55L STP85NF55L Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature. . . 5/10 STB85NF55L STP85NF55L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/10 STB85NF55L STP85NF55L D2PAK MECHANICAL DATA DIM. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 mm. MIN. 4.4 2.49 0.03 0.7 1.14 0.45 1.21 8.95 7.6 10 8.1 4.88 15 1.27 1.4 2.4 0.3 0° 0.4 8.5 8 TYP. MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 8.4 10.4 8.9 5.28 15.85 1.4 1.75 3.2 0.5 8° MIN. 0.173 0.098 0.001 0.028 0.045 0.018 0.048 0.352 0.299 0.394 0.318 0.192 0.591 0.050 0.055 0.094 0.012 0° 0.016 0.


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