SPU21N05L

SPD21N05L SPU21N05L SIPMOS ® Power Transistor N channel Enhancement mode Logic Level Avalanche-rated dv /dt rated 175°C operating temperature Pin 1 Pin 2 Pin 3 G D S Type VDS 55 V 55 V ID 20 A 20 A RDS(on) 0.07 Ω 0.07 Ω Package Ordering Code SPD21N05L SPU21N05L P-TO252 P-TO251 Q67040 - S4137- A2 Q67040 - S4131 - A2 Maximum Ratings Parameter Symbol Values Unit Continuous drain current TC = 25 °C TC = 100 °C ID A 20 14 Pulsed drain current TC = 25 °C IDpuls 80 EAS Avalanche energy, single pulse ID = 20 A, V DD = 25 V, RGS = 25 Ω L = 450 µH, Tj = 25 °C mJ 90 IAR EAR Avalanche current,limited by Tjmax Avalanche energy,periodic limited by Tjmax Reverse diode dv/dt IS = 20 A, VDS = 40 V, diF/dt = 200 A/µs Tjmax = 175 °C 20 5.5 A mJ kV/µs dv /dt 6 VGS Ptot Gate source voltage Power dissipation TC = 25 °C ± 14 55 V W Semiconductor Group 1 29/Jan/1998 SPD21N05L SPU21N05L Maximum Ratings Parameter Symbol Values Unit Operating temperature Storage temperature Thermal resistance, junction - case Thermal resistance, junction - ambient (PCB mount)** Thermal resistance, junction - ambient IEC climatic category, DIN IEC 68-1 Tj Tstg RthJC RthJA RthJA -55 ... + 175 -55 ... + 175 °C ≤ 2.7 ≤ 50 ≤ 100 55 / 175 / 56 K/W ** when mounted on 1 " square PCB ( FR4 );for recommended footprint Electrical Characteristics, at Tj = 25°C, unless otherwise specified Parameter Symbol min. Static Characteristics Values typ. max. Unit Drain- source breakd...