K4H561638F

DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM 256Mb F-die DDR SDRAM Specification Revision 1.3 October, 2004 Rev. 1.3 October, 2004 DDR SDRAM 256Mb F-die (x8, x16) 256Mb F-die Revision History Revision 1.0 (June, 2003) - First version for internal review Revision 1.1 (Agust, 2003) - Added x8 org (K4H560838F) and speed AA Revision 1.2 (May, 2004) - Modified IDD current spec. Revision 1.3 (October, 2004) - Corrected typo. DDR SDRAM Rev. 1.3 October, 2004 DDR SDRAM 256Mb F-die (x8, x16) Key Features Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe L(U)DQS Four banks operation Differential clock inputs(CK and CK) DLL aligns DQ and DQS transition with CK transition MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) All inputs except data & DM are sampled at the positive going edge of the system clock(CK) Data I/O transactions on both edges of data strobe Edge aligned data output, center aligned data input LDM,UDM for write masking only (x16) Auto & Self refresh 7.8us refresh interval(8K/64ms refresh) Maximum burst refresh cycle : 8 66pin TSOP II package DDR SDRAM Ordering Information Part No. K4H561638F-TC/LB3 K4H561638F-TC/LAA K4H561638F-TC/LA2 K4H561638F-TC/LB0 K4H560838F-TC/LB3 K4H560838F-TC/LAA K4H560838F-TC/LA2 K4H560838F-TC/LB0 32M x 8 16M x 16 Org. Max Freq. B3(DDR333@CL=2.5) AA(DDR266@CL=2) A2(DDR266@CL=2) B0(DDR266@C...