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STD12N05L Dataheets PDF



Part Number STD12N05L
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description N-CHANNEL POWER MOSFET
Datasheet STD12N05L DatasheetSTD12N05L Datasheet (PDF)

STD12N05L STD12N06L N - CHANNEL ENHANCEMENT MODE LOW THRESHOLD POWER MOS TRANSISTOR TYPE STD12N05L STD12N06L s s s s s s s s V DSS 50 V 60 V R DS( on) < 0.15 Ω < 0.15 Ω ID 12 A 12 A s s TYPICAL RDS(on) = 0.115 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW GATE CHARGE LOGIC LEVEL COMPATIBLE INPUT 175oC OPERATING TEMPERATURE APPLICATION ORIENTED CHARACTERIZATION THROUGH-HOLE IPAK (TO-251) POWER PACKAGE IN TUBE (SUFFIX ”-1”) SURFACE-MOUNTING DPAK (.

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STD12N05L STD12N06L N - CHANNEL ENHANCEMENT MODE LOW THRESHOLD POWER MOS TRANSISTOR TYPE STD12N05L STD12N06L s s s s s s s s V DSS 50 V 60 V R DS( on) < 0.15 Ω < 0.15 Ω ID 12 A 12 A s s TYPICAL RDS(on) = 0.115 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW GATE CHARGE LOGIC LEVEL COMPATIBLE INPUT 175oC OPERATING TEMPERATURE APPLICATION ORIENTED CHARACTERIZATION THROUGH-HOLE IPAK (TO-251) POWER PACKAGE IN TUBE (SUFFIX ”-1”) SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX ”T4”) 3 1 IPAK TO-251 (Suffix ”-1”) 2 1 DPAK TO-252 3 (Suffix ”T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SOLENOID AND RELAY DRIVERS s REGULATORS s DC-DC & DC-AC CONVERTERS s MOTOR CONTROL, AUDIO AMPLIFIERS s AUTOMOTIVE ENVIRONMENT (INJECTION, ABS, AIR-BAG, LAMPDRIVERS, Etc.) ABSOLUTE MAXIMUM RATINGS Symbol Parameter STD12N05L VD S V DG R V GS ID ID ID M( •) P tot T stg Tj Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 kΩ ) Gate-source Voltage Drain Current (continuous) at T c = 25 C Drain Current (continuous) at T c = 100 oC Drain Current (pulsed) Total Dissipation at Tc = 25 C Derating Factor Storage Temperature Max. Operating Junction Temperature o o Value STD12N06L 60 60 ± 15 12 8 48 45 0.3 -65 to 175 175 Unit 50 50 V V V A A A W W/o C o o C C (•) Pulse width limited by safe operating area November 1996 1/10 STD12N05L/STD12N06L THERMAL DATA R thj-cas e Rthj- amb Rt hc- sin k Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Resistance Case-sink Maximum Lead Temperature For Soldering Purpose Max Max Typ 3.33 100 1.5 275 o o C/W C/W o C/W o C AVALANCHE CHARACTERISTICS Symbol IA R E AS E AR IA R Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max, δ < 1%) Single Pulse Avalanche Energy (starting T j = 25 o C, ID = I AR, VD D = 25 V) Repetitive Avalanche Energy (pulse width limited by T j max, δ < 1%) Avalanche Current, Repetitive or Not-Repetitive (T c = 100 o C, pulse width limited by T j max, δ < 1%) Max Value 12 30 7 8 Unit A mJ mJ A ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbol V( BR)DSS Parameter Drain-source Breakdown Voltage Test Conditions I D = 250 µ A VG S = 0 for STD12N05L for STD12N06L T c = 125 oC Min. 50 60 1 10 ± 100 Typ. Max. Unit V V µA µA nA I DS S IG SS Zero Gate Voltage V DS = Max Rating Drain Current (V GS = 0) V DS = Max Rating x 0.8 Gate-body Leakage Current (V D S = 0) V GS = ± 15 V ON (∗ ) Symbol V G S(th) R DS( on) I D( on) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 5 V Test Conditions ID = 250 µ A ID = 6 A 12 Min. 1 Typ. 1.6 0.115 Max. 2.5 0.15 Unit V Ω A V DS > ID( on) x RD S(on) max V GS = 10 V DYNAMIC Symbol gfs ( ∗ ) C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions V DS > ID( on) x RD S(on) max V DS = 25 V f = 1 MHz ID = 6 A VG S = 0 Min. 4 Typ. 8 350 150 50 500 200 80 Max. Unit S pF pF pF 2/10 STD12N05L/STD12N06L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol t d(on) tr (di/dt) on Parameter Turn-on Time Rise Time Turn-on Current Slope Test Conditions V DD = 25 V ID = 6 A VGS = 5 V R G = 50 Ω (see test circuit, figure 3) V DD = 40 V ID = 12 A VGS = 5 V R G = 50 Ω (see test circuit, figure 5) V DD = 40 V ID = 12 A V GS = 5 V Min. Typ. 55 180 120 Max. 80 260 Unit ns ns A/ µ s Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge 12 6 5 18 nC nC nC SWITCHING OFF Symbol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions V DD = 40 V ID = 12 A R G = 50 Ω VGS = 5 V (see test circuit, figure 5) Min. Typ. 40 60 110 Max. 60 90 160 Unit ns ns ns SOURCE DRAIN DIODE Symbol IS D I SDM( • ) VS D (∗ ) t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 12 A VG S = 0 75 0.15 4 I SD = 12 A di/dt = 100 A/ µ s V DD = 25 V T j = 150 o C (see test circuit, figure 5) Test Conditions Min. Typ. Max. 12 48 1.5 Unit A A V ns µC A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Areas Thermal Impedance 3/10 STD12N05L/STD12N06L Derating Curve Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage 4/10 STD12N05L/STD12N06L Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Turn-on Current Slope Turn-off Drain-source Voltage Slope Cross-over Time 5/10 STD12N05L/STD12N06L Switching Safe Operating Area Accidental Overload Area Source-drain Diode Forward Characteristics Fig. 1: Unclamped Inductive Load Test Circuits Fig. 2: Un.


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