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MN61113 Dataheets PDF



Part Number MN61113
Manufacturers Panasonic Semiconductor
Logo Panasonic Semiconductor
Description 2K-Bit EEPROMs
Datasheet MN61113 DatasheetMN61113 Datasheet (PDF)

EEPROMs MN61113, MN61113S 2K-Bit EEPROMs Overview The MN61113 and MN61113S are 2048-bit, bit sequential EEPROMs with built-in address counters. They sequentially increment the address with the clock input to produce serial output. They include built-in charge pump circuit and timer for automatically erasing, writing, and modifying data using only a single 3 volt power supply. To reduce write times, they include a block write function for writing up to 32 bits at a time. This function makes it p.

  MN61113   MN61113



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EEPROMs MN61113, MN61113S 2K-Bit EEPROMs Overview The MN61113 and MN61113S are 2048-bit, bit sequential EEPROMs with built-in address counters. They sequentially increment the address with the clock input to produce serial output. They include built-in charge pump circuit and timer for automatically erasing, writing, and modifying data using only a single 3 volt power supply. To reduce write times, they include a block write function for writing up to 32 bits at a time. This function makes it possible to rewrite the contents of all 2048 bits within 1 second (typ.). Pin Assignment MN61113 MN61113S DIP008-P-0300A SOP008-P-0225 DATA CE VCC GND 1 2 3 4 8 7 6 5 OE RST CLK PGM Features 2048 words × 1 bit organization Built-in reset function Tristate output Low power consumption • 3 volt read: 1.5 mW (max.) • 3 volt program: 6 mW (max.) • 3 volt standby: 60 µW (max.) Single 3 volt power supply (charge pump circuit built in) Self timer for use in automatically erasing and writing data Built-in data polling function Write cycles: 105 times Data storage interval: 10 years Pull-up resistor on CE pin. Pull-down resistors on PGM, CLK, and RST pins (TOP VIEW) Applications Personal wireless equipment, cordless telephones, storage for recognition and adjustment data for terminals, etc. 1 MN61113, MN61113S Block Diagram EEPROMs Data latch pump Clock generator 8-bit counter CLK 6 Row decoder 64 × 16 cell matrix 3 VCC GND 4 RST 7 CE OE PGM 2 8 5 Control logic Column decoder Column gate VPP generator Timer Data I/O buffer 2 DATA 1 EEPROMs Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 Symbol DATA CE VCC GND PGM CLK RST OE Pin Name Data I/O Chip enable Power supply voltage Ground Program Clock input Reset input Output enable MN61113, MN61113S Electrical Characteristics VCC=2.6 to 3.5V, Ta=–10˚C to +60˚C 3 Volt Operation Parameter Power supply voltage "L" level input leakage current "H" level input leakage current Output leakage current "L" level input voltage "H" level input voltage VCC power supply current (during operation) VCC power supply current (during standby) "L" level output voltage "H" level output voltage Symbol VCC ILIL ILIH ILO VIL VIH ICC Test Conditions Read mode Program mode CE pin Other pins PGM, CLK, and RST pins Other pins min 2.6 3.0 –50 –10 — –10 — – 0.1 0.8 VCC max 3.5 3.5 — 10 –20 10 10 0.2 VCC VCC +0.3 500 2000 20 Unit V µA µA µA V V Read mode CLK;f=250kHz Program mode — — — µA ISB CE = VCC+ 0.3 V; RST and PGM pins at VCC; CLK pin open µA VOL VOH IOL=400µA IOH=10µA — VCC – 0.3 0.3 — V V 3 MN61113, MN61113S Function Descriptions Operating Modes Pin Symbol (Pin No.) Operating Mode EEPROMs CE (2) OE (8) VIL × VIH PGM (5) × × DATA (1) DOUT High-impedance DIN Read Standby Program VIL VIH VIL 4 EEPROMs Package Dimensions (Unit:mm) MN61113 DIP008-P-0300A MN61113, MN61113S 8 5 3.30±0.20 6.40±0.20 7.62±0.20 1 9.60±0.40 4 4.80 max. 3.45±0.30 2.54 0.50±0.10 0.70±0.10 1.30±0.10 0.70 min. SEATING PLANE MN61113S SOP008-P-0225 SEE DETAIL F 1.90 DETAIL F 1.10±0.20 0.30 SEATING PLANE 1.50±0.20 8 5 6.50±0.30 4.30±0.20 0.60 1 5.00±0.20 4 1.27 SEATING PLANE 0.40±0.10 0° to 1 5° 0.25 –0.05 +0.20 5 .


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