Document
ICX207AK
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for PAL Color Video Cameras
Description The ICX207AK is an interline CCD solid-state image sensor suitable for PAL color video cameras. Compared with the current product ICX087AK, sensitivity and saturation signal are improved drastically through the adoption of Super HAD CCD technology. Ye, Cy, Mg, and G complementary color mosaic filters are used. This chip features a field period readout system and an electronic shutter with variable charge-storage time. The package is a 10mm-square 14-pin DIP (Plastic). Features • High sensitivity (+6dB compared with ICX087AK) • High saturation signal (+2.2dB compared with ICX087AK) • Horizontal register: 3.3 to 5.0V drive • Reset gate: 3.3 to 5.0V drive • No voltage adjustment (Reset gate and substrate bias are not adjusted.) • Low smear and low dark current • Excellent antiblooming characteristics • Continuous variable-speed shutter • Recommended range of exit pupil distance: –20 to –100mm • Ye, Cy, Mg, and G complementary color mosaic filters on chip Device Structure • Interline CCD image sensor • Image size: • Number of effective pixels: • Total number of pixels: • Chip size: • Unit cell size: • Optical black: • Number of dummy bits: • Substrate material: 14 pin DIP (Plastic)
Pin 1 1
V
14 7 Pin 8 H 30
Optical black position (Top View)
Diagonal 4.5mm (Type 1/4) 500 (H) × 582 (V) approx. 290K pixels 537 (H) × 597 (V) approx. 320K pixels 4.47mm (H) × 3.80mm (V) 7.3µm (H) × 4.7µm (V) Horizontal (H) direction: Front 7 pixels, rear 30 pixels Vertical (V) direction: Front 14 pixels, rear 1 pixel Horizontal 16 Vertical 1 (even fields only) Silicon
∗Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97133C99
ICX207AK
VOUT
GND
Vφ1
Vφ2
Vφ 3
7
6
5
4
3
2
Cy
Ye G Ye Mg Ye G
Cy Mg Cy G Cy Mg
Ye G Ye Mg Ye G
Vertical Register
Mg Cy G Cy Mg
Horizontal Register Note) : Photo sensor
8
9
10
11
12
13
GND
VDD
Pin Description Pin No. 1 2 3 4 5 6 7 Symbol Vφ4 Vφ3 Vφ2 Vφ1 NC GND VOUT GND Signal output Description
φSUB
Pin No. 8 9 10 11 12 13 14
Hφ1
Hφ2
RG
VL
Vφ 4
1 Note) 14
NC
Block Diagram and Pin Configuration (Top View)
Symbol VDD GND φSUB VL RG Hφ1 Hφ2
Description Supply voltage GND Substrate clock Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock
Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock
Absolute Maximum Ratings Item VDD, VOUT, RG – φSUB Against φSUB Vφ1, Vφ3 – φSUB Vφ2, Vφ4, VL – φSUB Hφ1, Hφ2, GND – φSUB VDD, VOUT, RG – GND Against GND Vφ1, Vφ2, Vφ3, Vφ4 – GND Hφ1, Hφ2 – GND Against VL Vφ1, Vφ3 – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Between input clock pins Storage temperature Operating temperature ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –2– Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4 Ratings –40 to +8 –50 to +15 –50 to +0.3 –40 to +0.3 –0.3 to +18 –10 to +18 –10 to +6 –0.3 to +28 –0.3 to +15 to +15 –5 to +5 –13 to +13 –30 to +80 –10 to +60 Unit V V V V V V V V V V V V °C °C ∗1 Remarks
ICX207AK
Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL φSUB φRG Min. 14.55 Typ. 15.0 ∗1 ∗2 ∗2 Max. 15.45 Unit V Remarks
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol IDD Min. Typ. 3 Max. 5 Unit mA Remarks
Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VφV Vertical transfer clock voltage VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage VφH VHL VφRG Reset gate clock voltage VRGLH – VRGLL VRGL – VRGLm Substrate clock voltage VφSUB 21.0 22.0 3.0 –0.05 3.0 3.3 0 3.3 Min. 14.55 –0.05 –0.2 –8.0 6.3 –0.25 –0.25 Typ. 15.0 0 0 –7.0 7.0 Max. 15.45 0.05 0.05 –6.5 8.05 0.1 0.1 0.3 0.3 0.3 0.3 5.25 0.05 5.5 0.4 0.5 23.5 Unit V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Input through 0.1µF capacitance Low-level coupling Low-level coupling High-level co.