Document
5800 AND 5801 BiMOS II LATCHED DRIVERS
5800 AND 5801
BiMOS II LATCHED DRIVERS
The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (‘D’ type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar npn Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or microprocessor I/O. The UCN5800A and UCN5800L each contain four latched drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight latched drivers. The UCN5800A/L and UCN5801A/EP/LW supersede the original BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These second-generation devices are capable of much higher data input rates and will typically operate at better than 5 MHz with a 5 V logic supply. Circuit operation at 12 V affords substantial improvement over the 5 MHz figure. The CMOS inputs are compatible with standard CMOS and NMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small dc motors, etc. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 500 mA and will withstand at least 50 V in the OFF state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. The UCN5800A is furnished in a standard 14-pin DIP; the UCN5800L and UCN5801LW in surface-mountable SOICs; the UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the UCN5801EP in a 28-lead PLCC.
Data Sheet 26180.10B
UCN5800L
1 14
UCN5800A
CLEAR STROBE IN 1 IN 2 IN 3 IN 4 GROUND 1 2 3 4 5 6 7 14 VDD 13 12 OUTPUT ENABLE SUPPLY OUT 1 OUT 2 OUT 3 OUT 4 COMMON
LATCHES
11 10 9 8
Dwg. PP-014A
Note the UCN5800A (DIP) and the UCN5800L (SOIC) are electrically identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS at +25 °C Free-Air Temperature
Output Voltage, VCE . . . . . . . . . . . . . . 50 V Supply Voltage, VDD . . . . . . . . . . . . . . 15 V Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Continuous Collector Current, lC . . . . . . . . . . . . . . . . . . . . . . 500 mA Package Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . . . -55°C to +150°C
Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.
FEATURES
s Output Transient Protection s To 4.4 MHz Data Input Rate s Internal Pull-Down Resistors s High-Voltage, s Low-Power CMOS Latches High-Current Outputs s Automotive Capable s CMOS, NMOS, TTL Compatible Inputs
Always order by complete part number, e.g.,
UCN5801EP .
5800 AND 5801 BiMOS II LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
SUPPLY VDD COMMON
IN N OUT N STROBE
CLEAR GROUND OUTPUT ENABLE
COMMON MOS CONTROL
TYPICAL MOS LATCH
TYPICAL BIPOLAR DRIVE
Dwg. FP-016-1
TYPICAL INPUT CIRCUIT
VDD
2.5
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
28-LEAD PLCC, R θJA = 55°C/W 14-PIN DIP, R θJA = 60°C/W
22-PIN DIP, R θJA = 50°C/W
2.0
IN
1.5
24-LEAD SOIC, R θJA = 68°C/W
1.0
Dwg. EP-010-4A
0.5
14-LEAD SOIC, R θJA = 95°C/W
0
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-023-1
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1985, 1997, Allegro MicroSystems, Inc.
5800 AND 5801 BiMOS II LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Characteristic Output Leakage Current Symbol I CEX Test Conditions VCE = 50 V, TA = +25°C VCE = 50 V, TA = +70°C Collector-Emitter Saturation Voltage VCE(SAT) IC = 100 mA IC = 200 mA IC = 350 mA, VDD = 7.0 V Input Voltage VIN(0) VIN(1) VDD = 12 V VDD = 10 V VDD = 5.0 V (See Note) Input Resistance rIN VDD = 12 V VDD = 10 V VDD = 5.0 V Supply Current I DD(ON) (Each Stage) IDD(OFF) (Total) Clamp Diode Leakage Current Clamp Diode Forward Voltage IR VDD = 12 V, Outputs Open VDD = 10 V, Outputs Open VDD = 5.0 V, Outputs Open VDD = 12 V, Outputs Open, Inputs = 0 V VDD = 5.0 V, Outputs Open, Inputs = 0 V VR = 50 V, TA = +25°C VR = 50 V, TA = +70°C VF IF = 350 mA Min. — — — — — — 10.5 8.5 3.5 50 50 50 — — — — — — — — Typ. — — 0.9 1.1 1.3 — — — — 200 300 600 1.0 0.9 0.7 — 50 — — 1.7 Limits Max. 50 100 1.1 1.3 1.6 1.0 — — — — — — 2.0 1.7 1.0 200 100 50 100 2.0 Units µA µA V V V V V V V kΩ kΩ kΩ mA mA mA µA µA µA µA V
NOTE: Operation of these devices with standard TTL or D.