Document
5816
4-TO-16 LINE LATCHED DECODER/DRIVERS
5816
Data Sheet 26186.10
4-TO-16 LINE LATCHED DECODER/DRIVERS
DIODE 0-7 COMMON OUT0 OUT1
OUT2
OUT3 OUT4
OUT 5
ABSOLUTE MAXIMUM RATINGS at TA = 25°C
Output Voltage, VCE . . . . . . . . . . . . . . 60 V Logic Supply Voltage, VDD . . . . . . . . . 15 V Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Output Current, IC . . . . . . . . . . . . . 500 mA Package Power Dissipation, PD . . . . . . . . . . . . . . . . . . . See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . . -55°C to +150°C
Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.
T C U Y D L O N R O P E D C E N U E N ER I T N EF O R C R S I O D F —
OUTPUT ENABLE LOGIC SUPPLY STROBE CHIP ENABLE IN D IN C 28 27 V DD OE ST 26 4 3 2 1 IN B
5 6 7 8 9 K LATCHES 25 IN A K 24 DIODE 8-15 COMMON OUT 15 23 22 OUT 14 DECODER 21 OUT 13 10 11 20 OUT 12
UCN5816EP
The UCN5816A and UCN5816EP 4-to-16 line latched decoder/ drivers combine low-power CMOS inputs and logic with 16 highcurrent, high-voltage bipolar outputs. The CMOS inputs cause minimal loading and are compatible with standard CMOS, PMOS, and NMOS logic. TTL or DTL circuits may require the use of appropriate pull-up resistors to ensure an input logic high. The logic operates over a supply range of 5 V to 12 V. A CHIP ENABLE function can be used with two devices for 5-to-32 line decoding applications. The 16 bipolar power outputs are open-collector 60 V Darlington drivers capable of sinking 350 mA continuously. Internal transientsuppression diodes provide protection for use with inductive loads. For ink-jet printer applications, the A5817SEP addressable 28-line decoder/driver is recommended.
19
OUT 11
Dwg. PP-030
The UCN5816A is supplied in a 28-pin dual in-line plastic package with 0.600" (15.24 mm) row spacing. The UCN5816EP is furnished in a 28-lead plastic chip carrier (quad pack) for minimum-area surfacemount applications. Both devices will drive 350 mA loads continuously over the full operating temperature range.
OUT 7 13
OUT 6 12
15
17
GROUND
GROUND
OUT 10 18
OUT 8 16
14
OUT 9
FEATURES
s s s s s s
Addressable Data Entry 60 V Minimum Output Breakdown CMOS, PMOS, NMOS, TTL Compatible Inputs Low-Power CMOS Logic and Latches Output Transient Protection Output Enable and Strobe Functions
Always order by complete part number: Part Number UCN5816A UCN5816EP Package 28-Pin DIP 28-Lead PLCC
5816
4-TO-16 LINE LATCHED DECODER/DRIVERS
UCN5816A
GROUND CHIP ENABLE STROBE LOGIC SUPPLY OUTPUT ENABLE DIODE 0-7 COMMON OUT 0 OUT 1 OUT 2 OUT 3 1 2 3 4 5 6 7 8 9 10 CE ST V DD OE K DECODER K LATCHES 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GROUND IND IN C INB IN A DIODE 8-15 COMMON OUT15 OUT14 OUT13 OUT 12 OUT11 OUT10 OUT 9 OUT 8
3.0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
IX FF SU R ', 'A
2.0
A θJ
= /W °C 45
1.5
IX FF SU ,R P' 'E
1.0
θJ A
= /W °C 55
OUT 4 11 OUT 5 12
0.5
OUT 6 13 OUT 7 14
Dwg. PP-031
0 25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-028-1A
TYPICAL INPUT CIRCUITS
VDD
V DD
TYPICAL OUTPUT DRIVER
K
IN
IN
OUT
Dwg. EP-010-4A
Dwg. EP-010-3
Dwg. EP-021-4
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 W Copyright © 1984, 1995, Allegro MicroSystems, Inc.
5816
4-TO-16 LINE LATCHED DECODER/DRIVERS
ELECTRICAL CHARACTERISTICS at TA = 25°C, VDD = 5 V (unless otherwise specified).
Characteristic Output Leakage Current Output Saturation Voltage Symbol ICEX VCE(SAT) Test Conditions VCE = 60 V, TA = +25°C IC = 100 mA IC = 200 mA IC = 350 mA, VDD = 7.0 V Input Voltage VIN(0) VIN(1) VDD = 12 V VDD = 5.0 V Input Resistance RIN VDD = 12 V VDD = 5.0 V Supply Current IDD(ON) VDD = 12 V, Outputs Open VDD = 5.0 V, Outputs Open IDD(OFF) All Drivers OFF, All Inputs = 0 V, OE = VDD = 5.0 V All Drivers OFF, All Inputs = 0 V, OE = VDD = 12 V Clamp Diode Leakage Current Clamp Diode Forward Voltage VF IR VR = 60 V, TA = +25°C VR = 60 V, TA = +70°C IF = 350 mA Min. — — — — -0.3 10.5 3.5 50 100 — — — — — — — Limits Typ. Max. — 0.9 1.1 1.3 — — — 200 600 2.0 1.0 — — — — 1.5 50 1.1 1.3 1.6 0.8 — 5.3 — — 3.0 1.5 100 200 50 100 2.0 Units µA V V V V V V kΩ kΩ mA mA µA µA µA µA V
5816
4-TO-16 LINE LATCHED DECODER/DRIVERS
CLEAR F
STROBE A OUTPUT ENABLE INN D OUTN E E C B C B A C B
G
G
p/o Dwg. No. A-10,895A
TIMING CONDITIONS
(Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns B. Minimum Data Active Time After Strobe Disabled (Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns C. Minimum Strobe Pulse Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns D. Typical Time Between Strobe Activation and Output On.