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UCN5821 Dataheets PDF



Part Number UCN5821
Manufacturers Allegro
Logo Allegro
Description (UCN5822) BiMOS II 8-BIT SERIAL-INPUT / LATCHED DRIVERS
Datasheet UCN5821 DatasheetUCN5821 Datasheet (PDF)

5821 AND 5822 BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS A merged combination of bipolar and MOS technology gives these devices an interface flexibility beyond the reach of standard logic buffers and power driver arrays. The UCN5821A, UCN5821LW, UCN5822A, and UCN5822LW each have an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The UCN5821A/LW and UCN5822A/LW are identical except for rated output .

  UCN5821   UCN5821


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5821 AND 5822 BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS A merged combination of bipolar and MOS technology gives these devices an interface flexibility beyond the reach of standard logic buffers and power driver arrays. The UCN5821A, UCN5821LW, UCN5822A, and UCN5822LW each have an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The UCN5821A/LW and UCN5822A/LW are identical except for rated output voltage. BiMOS II devices have much higher data-input rates than the original BiMOS circuits. With a 5 V logic supply, they will typically operate at better than 5 MHz. With a 12 V supply, significantly higher speeds are obtained. The CMOS inputs are compatible with standard CMOS and NMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, the drivers can be cascaded for interface applications requiring additional drive lines. The UCN5821/22A are furnished in a standard 16-pin plastic DIP; the UCN5821/22LW are in a 16-lead wide-body SOIC for surface-mount applications. The UCN5821A is also available for operation from -40°C to +85°C. To order, change the prefix from ‘UCN’ to ‘UCQ’. Data Sheet 26185.12E CLOCK SERIAL DATA IN LOGIC GROUND LOGIC SUPPLY SERIAL DATA OUT STROBE OUTPUT ENABLE POWER GROUND 1 2 3 4 5 6 7 8 CLK 16 15 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 SHIFT REGISTER 14 LATCHES VDD 13 12 11 10 9 ST OE SUB Dwg. PP-026A Note the DIP package and the SOIC package are electrically identical and share common terminal number assignments. ABSOLUTE MAXIMUM RATINGS at 25°C Free-Air Temperature Output Voltage, VOUT UCN5821A & UCN5821LW ..... 50 V UCN5822A & UCN5822LW ..... 80 V Logic Supply Voltage, VDD ............. 15 V Input Voltage Range, VIN .................. -0.3 V to VDD + 0.3 V Continuous Output Current, IOUT ..................................... 500 mA Package Power Dissipation, PD Package Code ‘A’ .................. 2.1 W Package Code ‘LW’ ............... 1.5 W Operating Temperature Range, TA ............................ -20°C to +85°C Storage Temperature Range, TS .......................... -55°C to +150°C Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. FEATURES I To 3.3 MHz Data Input Rate I CMOS, NMOS, TTL Compatible I Internal Pull-Down Resistors I Low-Power CMOS Logic & Latches I High-Voltage Current-Sink Outputs I Automotive Capable Always order by complete part number, e.g., UCN5821A . www.allegromicro.com 5821 AND 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS TYPICAL INPUT CIRCUITS V DD CLOCK SERIAL DATA IN LOGIC GROUND 1 FUNCTIONAL BLOCK DIAGRAM VDD 4 LOGIC SUPPLY SERIAL DATA OUT STROBE OUTPUT ENABLE (ACTIVE LOW) 2 SERIAL-PARALLEL SHIFT REGISTER 5 3 LATCHES 6 IN 7 STROBE & OUTPUT ENABLE 16 15 14 13 12 11 10 9 MOS BIPOLAR 8 POWER GROUND Dwg. FP-013A SUB OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 Dwg. EP-010-3 NOTE — There is an indeterminate resistance between logic ground and power ground. For proper operation, these terminals must be externally connected together. VDD CLOCK & SERIAL DATA IN IN Number of Outputs ON (IOUT = 200 mA VDD = 12 V) 8 7 6 5 4 3 2 1 UCN5821A Max. Allowable Duty Cycle at Ambient Temperature of 25°C 40°C 50°C 60°C 70°C 90% 100% 100% 100% 100% 100% 100% 100% 79% 90% 100% 100% 100% 100% 100% 100% 72% 82% 96% 100% 100% 100% 100% 100% 65% 74% 86% 100% 100% 100% 100% 100% 57% 65% 76% 91% 100% 100% 100% 100% Dwg. EP-010-4A TYPICAL OUTPUT DRIVER OUT Number of Outputs ON (IOUT = 200 mA VDD = 12 V) 8 7 6 5 4 3 2 1 UCN5821LW Max. Allowable Duty Cycle at Ambient Temperature of 25°C 40°C 50°C 60°C 70°C 67% 77% 90% 100% 100% 100% 100% 100% 59% 68% 79% 95% 100% 100% 100% 100% 54% 62% 72% 86% 100% 100% 100% 100% 49% 56% 65% 78% 98% 100% 100% 100% 43% 49% 57% 68% 86% 100% 100% 100% 7.2K 3K SUB Dwg. No. A-14,314 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1985, 2000, Allegro MicroSystems, Inc. 5821 AND 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, (unless otherwise specified). Limits Characteristic Output Leakage Current Symbol ICEX Test Conditions UCN5821A/LW, VOUT = 50 V UCN5822A/LW, VOUT = 80 V UCN5821A/LW, VOUT = 50 V, TA = +70°C UCN5822A/LW, VOUT = 80 V, TA = +70°C Collector-Emitter Saturation Voltage VCE(SAT) IOUT = 100 mA IOUT = 200 mA IOUT = 350 mA, VDD = 7.0 V Input Voltage VIN(0) VIN(1) VDD = 12 V VDD = 5.0 V Input Resistance rIN VDD = 12 V VDD = 5.0 V Supply Current IDD(ON) One Driver ON, VDD = 12 V One Driver ON, VDD = 10 V One Driver ON, VDD = 5.0 V IDD(OFF) VDD = 5.0 V, All Drivers OFF, All Inputs = 0 V VDD = 12 V, All Drivers OFF, All Inputs = 0 V Min. — — — — — — — — 10.5 3.5 50 50 — — — — — Max. 50 50 100 100 1.1 1.3 1.6 0.8 — — — — 4.5 3.9 2.4 1.6 2.9 Units µA µA µA µA .


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