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SP8121 Monolithic, 12–Bit Data Acquisition System
s Complete Monolithic 8-Channel, 12-Bit DAS s 100kHz Throughput s 16-Bit Microprocessor Bus Interface s Parallel 12-Bit Output s Latched MUX Address s Tri-State Latched Output s No Missing Codes to 12-Bits s 32-pin SOIC and PDIP Available s 200mW Power Dissipation Maximum
* Formerly part of the SP410 Series.
DESCRIPTION The SP8121 is a complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted in 12-bit parallel. The SP8121 is available in 32-pin plastic DIP or SOIC packages, operating over the commercial temperature range.
MULTIPLEXER
12-BIT A/D CONVERTER
MUX DECODE
REFERENCE
CONTROL LOGIC
CLOCK
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
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TRI-STATE LATCH
© Copyright 2000 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
VCC to Common Ground .............................................. 0V to +16.5V VLOGIC to Common Ground ............................................... 0V to +7V Analog Common to Digital Common Ground ............... -0.5V to +1V Digital Inputs to Common Ground .................... -0.5V to VLOGIC+0.5V Digital Outputs to Common Ground ................. -0.5V to V LOGIC+0.5V Multiplexer Analog Inputs ...................................... -16.5V to +31.5V Gain and Offset Adjustment ................................ -0.5V to VCC+0.5V Analog Input Maximum Current ........................................... 100mA Temperature with Bias Applied ............................. -55°C to +125°C Storage Temperature ............................................ -65 °C to +150°C Lead Temperature, Soldering .................................... 300°C, 10sec
CAUTION: ESD (ElectroStatic Discharge) sensitive device. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are removed.
SPECIFICATIONS
(TA= 25°C and nominal supply voltages unless otherwise noted)
MIN. ANALOG INPUTS Input Voltage Range Multiplexer Inputs Configuration Input Impedance ON Channel OFF Channel Input Bias Current/Channel Crosstalk OFF to ON Channel
TYP. 0 to +5
MAX.
UNIT V
CONDITIONS
8 Single-ended 109 1010 +10 +250 -90 -80 -70 Ω Ω nA nA dB dB dB Bits LSB LSB LSB LSB LSB %FSR Parallel with 30pF Parallel with 5pF 25°C -55°C to +125°C 10kHz, 0V to +5VPk-to-pk 50kHz, 0V to +5VPk-to-pk 100kHz, 0V to +5VPk-to-pk
ACCURACY Resolution 12 Linearity Error –K +0.5 –J +1 Differential Non-Linearity –K +1 –J +2 +0.5 +4 Offset Error Gain Error +0.3 +1 No Missing Codes –K Guaranteed TRANSFER CHARACTERISTICS Throughput Rate 100 MUX Settling/Acquisition 1.9 A/D Conversion 8.1 STABILITY +0.5 +2.5 Linearity Offset +5 +25 Gain +10 +50 DIGITAL INPUTS Capacitance 5 Logic Levels VIH +2.4 +5.5 VIL -0.5 +0.8 IIH +5 IIL +5
Adjustable to zero Adjustable to zero
kHz µs µs ppm/°C ppm/°C ppm/°C pF V V µA µA
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
© Copyright 2000 Sipex Corporation
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SPECIFICATIONS (continued)
(TA= 25°C and nominal supply voltages unless otherwise noted)
MIN. TYP. MAX. DIGITAL OUTPUTS Capacitance 5 Logic Levels +2.4 VOH VOL +0.4 Leakage Current ±40 Data Output Positive true binary POWER REQUIREMENTS VLOGIC +4.5 +5.5 ILOGIC 0.8 4 VCC +11.4 +16.5 ICC 9 12 Power Dissipation 140 200 ENVIRONMENTAL AND MECHANICAL Operating Temperature Commercial (–J, –K) 0 +70 Storage Temperature -65 +150 Packages –_P 32–pin Plastic DIP –_S 32–pin SOIC
UNIT pF V V µA
CONDITIONS
IOH ≤ 500µA IOL ≤ 1.6mA High impedance, data bits only
V mA V mA mW
°C °C
SP8121DS/02
SP8121 Monolithic, 12-Bit Data Acquisition System
© Copyright 2000 Sipex Corporation
3
SP8121 PINOUT
DB11 (MSB)
SP8121 CONTROL TRUTH TABLE
CE
DB0 (LSB) LATCH
R/C 0 0 H ->L 1
OPERATION Start Conversion Start Conversion Start Conversion Enable 12-bit Output (when STATUS=0)
L->H 1 1
S
DB10
MA2
MA1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
MA0
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
CLOCK
REF 12-BIT ADC DECODE 8-CHANNEL MULTIPLEXER 5 6 7 8 9 10 11 12 13 14 15 16
1
CONTROL LOGIC 1 2 3 4
SP8121 MULTIPLEXER TRUTH TABLE
LATCH MA2 H -> L H -> L H -> L H -> L H -> L 0 0 0 0 1 1 1 1 X X MA1 0 0 1 1 0 0 1 1 X X MA0 0 1 0 1 0 1 0 1 X X OPERATION CHO Selected CH1 Selected CH2 Selected CH3 Selected CH4 Selected CH5 Selected CH6 Selected CH7 Selected Prev. CH “n” Held Prev. CH “n” Held
OFFSET ADJ.
ANA. IN. CH0
ANA. IN. CH1
ANA. IN. CH2
ANA. IN. CH3
ANA. IN. CH4
ANA. IN. CH5
ANA. IN. CH6
SP8121 PINOUT STATUS — Identifies valid data output; goes to logic high during conversion; goes to logic low when conversion is completed and data is va.