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M52036SP Dataheets PDF



Part Number M52036SP
Manufacturers Renesas Technology
Logo Renesas Technology
Description SYNC SIGNAL PROCESSOR
Datasheet M52036SP DatasheetM52036SP Datasheet (PDF)

M52036SP SYNC SIGNAL PROCESSOR REJ03F0086-0100Z Rev.1.0 Sep.22.2003 Description The M52036SP is a semiconductor integrated circuit for the automatic selection and rectification of sync waveforms. The IC operates with synchronizing signals in three forms, that is, separate sync(positive or negative polarity, 1 to 5 Vp-p), composite sync (positive or negative polarity, 1 to 5 Vp-p), and synchronous video (negative sync). This IC is optimal for processing sync signals for multi-scan-type displays..

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M52036SP SYNC SIGNAL PROCESSOR REJ03F0086-0100Z Rev.1.0 Sep.22.2003 Description The M52036SP is a semiconductor integrated circuit for the automatic selection and rectification of sync waveforms. The IC operates with synchronizing signals in three forms, that is, separate sync(positive or negative polarity, 1 to 5 Vp-p), composite sync (positive or negative polarity, 1 to 5 Vp-p), and synchronous video (negative sync). This IC is optimal for processing sync signals for multi-scan-type displays. Features • Indicates the presence or absence of synchronizing-signal input and the polarities of the signals • Pulse-output circuit is for open-collector output • Clamp-pulse output and Clamp-pulse trigger is generated at the front edge for separate sync and composite sync input, and at the rear edge for sync on video input. • 20-pin shrink-DIP Application • Display Monitor Recommended Operating Condition • Supply voltage range: 11 to 13 V • Rated supply voltage: 12 V Block Diagram Rev.1.0, Sep.22.2003, page 1 of 13 M52036SP Pin Functions Absolute Maximum Rating Item Supply voltage Power dissipation Operating ambient temperature Storing temperature Symbol Vcc Pd Topr Tstg Rated values 14.0 1000 –20 to 85 –40 to 150 Units V mW °C °C Rev.1.0, Sep.22.2003, page 2 of 13 M52036SP Electrical Characteristics (Ta = 25°C Vcc = 12 V, VDD = Open) Rev.1.0, Sep.22.2003, page 3 of 13 M52036SP Electrical Characteristics (cont.) (Ta = 25°C Vcc = 12 V, VDD = Open) Rev.1.0, Sep.22.2003, page 4 of 13 M52036SP Electrical Characteristics (cont.) (Ta = 25°C Vcc = 12 V, VDD = Open) Rev.1.0, Sep.22.2003, page 5 of 13 M52036SP Test Circuit Rev.1.0, Sep.22.2003, page 6 of 13 M52036SP Logic Table Table.1 Decoder Logic Output Input to pin 6 HD.COMP HD. COMP. (POS) HD. COMP. (POS) HD. COMP. (POS) HD. COMP. (NEG) HD. COMP. (NEG) HD. COMP. (NEG) NON NON NON Input to pin 8 VD NON VD (POS) VD (NEG) NON VD (POS) VD (NEG) NON VD (POS) VD (NEG) Output pins 1 H H H H H H L L L 2 L H H L H H L H H 18 L L L H H H L L L 19 L L H L L H L L H Table.2 Allowable Amplitude of Input Voltage Amplitude of input to pin 4 Amplitude of input to pin 6 Amplitude of input to pin 8 Table.3 Output Priority Input signals (pin) 4 pin 6 pin Ο Ο Ο Ο × × × × × Ο × Ο × Ο × Ο 8 pin × × Ο Ο × × Ο Ο Output signals (pin) 13 pin 14 pin 15 pin 4 11 6 11 4 8 6 8 × × 6 11 × 8 6 8 17 pin 4 6 4 6 × 6 × 6 Rev.1.0, Sep.22.2003, page 7 of 13 M52036SP Table.4 Pulse Duty Ratio for Allowable Maximum Input Signal Input Pulse to Pin 6 (HD.COMP.) FH = 16 kHz Maximum voltage amplitude (VP-P) POS. NEG. % Time (µs) % Time (µs) 1.0 15.0 9.38 15.0 9.38 3.3 13.8 8.63 13.0 8.13 4.0 11.2 7.00 10.5 6.56 5.0 9.0 8.63 8.8 5.50 Input Pulse to Pin 8 (VD) Fv = 60 Hz Maximum voltage amplitude (VP-P) POS. NEG. % Time (ms) % Time (ms) 1.0 14.1 2.35 14.8 2.47 3.3 12.1 2.02 11.3 1.88 4.0 9.8 1.63 9.2 1.53 5.0 7.7 1.28 7.5 1.25 Precautions for Application 1. Input 1) Green (Sync on Video) input (pins [3] and [4]) The input signals must be in sync negative polarity. For sync separation, a method is used in which the sync tip is clamped by a capacitor attached externally to pin [4] and by the C and R attached to pin [3]. Then sync tip of pin [4] shows approximately 4 V. Rev.1.0, Sep.22.2003, page 8 of 13 M52036SP 2) Comp Sync/H sync, V sync input Connect the composite sync input to pin [6]. For the separate sync input, connect H and V to pins[6] and [8] respectively. The bias and impedance at pins [6] and [8] are 6 V and 10 kΩ, respectively. Waveform shaping and polarity detection are performed by a double threshold converter installed inside. The internal circuit is as shown in Fig.B. The average DC voltage is set to approximately 0.7 V higher and lower than V2. Thus, as shown in Fig. A, this processor is energized by an input signal 0.7 Vp-p or over when the duty ratio is small. On the other hand, approximately 1.4 Vp-p is suitable when the duty ratio is large. Fig. C indicates an allowable standard value for the input duty. Rev.1.0, Sep.22.2003, page 9 of 13 M52036SP Fig. D shows an example of the measures for improving the allowable duty ratio in a range of 1.4 Vp-p or over of the input signal. For use in a range outside the specified value, confirm that the waveform complies with Fig. E when measured it after removing the filters in pins [7] and [9]. 3) Polarity detection and empty input detection (pins [7] and [9]) A capacitor is required to be installed external as a filter for polarity detection and empty input detection. The large the capacitance, the smaller the ripple and reduces malfunction. However, the detecting time is lengthened. For an input of 15 kHz, a capacitor of 0.05 µF or larger is recommended. For 60 Hz, a 10 µF or larger is sufficient. If it is necessary to use a capacitor of smaller capacitance, measure the waveform at the filter terminal under the condition of the lowest frequency of the input sync signal to be used and the smallest duty ratio. And make s.


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