Document
ICX099AL
1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras
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Description The ICX099AL is a 1/2-inch optical interline CCD solid-state image sensor with a square pixel array and 800K effective pixels. Progressive scan allows all pixels' signals to be output independently within approximately 1/15 second. Also, the adoption of high-speed mode supports 30 frames per second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize high resolution, full-frame still image without a mechanical shutter. Further, high sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as high resolution cameras for FA, etc. Features • Progressive scan allows individual readout of the image signals from all pixels. • High horizontal and vertical resolution still image without a mechanical shutter. • Supports 30 frames per second mode • Square pixel • Horizontal drive frequency: 14.31818MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • High resolution, high sensitivity, low dark current • Continuous variable-speed shutter • Low smear • Excellent antiblooming characteristics Device Structure • Interline CCD image sensor • Optical size: • Number of effective pixels: • Total number of pixels: • Chip size: • Unit cell size: • Optical black: • Number of dummy bits: • Substrate material: 20 pin DIP (Cer-DIP)
Pin 1 2
V
7 3 Pin 11 H 40
Optical black position (Top View)
1/2-inch format 1034 (H) × 779 (V) approx. 800K pixels 1077 (H) × 788 (V) approx. 850K pixels 7.60mm (H) × 6.20mm (V) 6.25µm (H) × 6.25µm (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 7 pixels, rear 2 pixels Horizontal 29 Vertical 1 Silicon
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E97747-PS
ICX099AL
Block Diagram and Pin Configuration (Top View)
GND
VOUT
GND
Vφ2B
Vφ2A
2
Vφ3
10
9
8
7
6
NC
5
4
3
Vertical register
Vφ1
1 Note)
NC
NC
Horizontal register
Note)
: Photo sensor
11
12
13
14
15
16
17
18
19
20
GND
φSUB
CSUB
φRG
VDD
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol Vφ1 Vφ2A NC Vφ2B NC Vφ3 GND GND NC VOUT Signal output Description
Pin No. 11 12 13
Symbol VDD GND φSUB CSUB NC NC VL φRG Hφ1 Hφ2
Hφ 1
Hφ 2
NC
NC
VL
Description Supply voltage GND Substrate clock Substrate bias∗1
Vertical register transfer clock Vertical register transfer clock
Vertical register transfer clock
14 15
Vertical r.