SN74LS74A

SN74LS74A Dual D−Type Positive Edge−Triggered Flip−Flop The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect. http://onsemi.com LOW POWER SCHOTTKY MODE SELECT − TRUTH TABLE OPERATING MODE INPUTS SD CD D OUTPUTS QQ Set Reset (Clear) *Undetermined Load “1” (Set) Load “0” (Reset) LHXHL HLXLH L L XHH HH h H L HH l LH * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage TA Operating Ambient Temperature Range 4.75 5.0 5.25 V 0 25 70 °C IOH Output Current − High IOL Output Current − Low ...