74F843

74F843 9-Bit Transparent Latch January 1988 Revised July 1999 74F843 9-Bit Transparent Latch General Description The 74F843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. Features s 3-STATE output Ordering Code: Order Number 74F843SC 74F843SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE Connection Diagram © 1999 Fairchild Semiconductor Corporation DS009453 www.fairchildsemi.com 74F843 Unit Loading/Fan Out U.L. Pin Names D0–D8 OE LE CLR PRE O0–O8 Description Data Inputs Output Enable Input Latch Enable Clear Preset 3-STATE Data Outputs 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/ −0.6 mA 20 µA/ −0.6 mA 20 µA/ −0.6 mA 20 µA/ −0.6 mA 20 µA/ −0.6 mA −3 mA/24 mA Functional Description The 74F843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus wh...