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INTEGRATED CIRCUITS
74F74 Dual D-type flip-flop
Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook 1996 Mar 12
Philips Semiconductors
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
FEATURE
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output. TYPE 74F74 TYPICAL fmax 125MHz
PIN CONFIGURATION
RD0 D0 CP0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RD1 D1 CP1 SD1 Q1 Q1
SF00045
TYPICAL SUPPLY CURRENT (TOTAL) 11.5mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F74N N74F74D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F74N I74F74D PKG. DWG. #
14-pin plastic DIP 14-pin plastic SO
SOT27-1 SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0, D1 CP0, CP1 SD0, SD1 RD0, RD1 Data inputs Clock inputs (active rising edge) Set inputs (active low) Reset inputs (active low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/3.0 1.0/3.0 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/1.8mA 20µA/1.8mA 1.0mA/20mA
Q0, Q1, Q0, Q1 Data outputs 50/33 NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC SYMBOL
2 12
IEC/IEEE SYMBOL
4 D0 D1 3 4 1 11 10 13 CP0 SD0 RD0 CP1 SD1 RD1 Q0 Q0 Q1 Q1 11 12 13 VCC = Pin 14 GND = Pin 7 5 6 9 8 10 3
S C1
&
5
2 1
1D R
6
S C2 2D R
9
8
SF00046
SF00047
1996 Mar 12
2
853 0335 16554
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS OUTPUTS D X X X h l X Q H L H H L NC Q L H H L H NC SD L RD H L L H H H CP X X X ↑ ↑ ↑ OPERATING MODE Asynchronous set Asynchronous reset Undetermined* Load ”1” Load ”0” Hold
SD
4, 10
RD
1, 13
5, 9 Q
H L H
CP
3, 11
6, 8
Q
H H
D
2, 12
VCC = Pin 14 GND = Pin 7
SF00048
NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition NC= No change from the previous setup X = Don’t care ↑ = Low-to-high clock transition ↑ = Not low-to-high clock transition * = This setup is unstable and will change when either set or reset return to the high leve.