74F640

74F640 74F645 Octal Bus Transceiver with 3-STATE Outputs July 1989 Revised August 1999 74F640 74F645 Octal Bus Transceiver with 3-STATE Outputs General Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive (T/R) input. The 74F645 is a high speed/low power version of the 74F245. The 74F640 is an inverting option of the 74F645. Features s Designed for asynchronous two-way data flow between busses s Outputs sink 64 mA s Transmit/receive (T/R) input controls the direction of data flow s 74F645 is a lower power, faster version of the 74F245 s 74F640 is an inverting option of the 74F645 Ordering Code: Order Number 74F640SC 74F640PC 74F645PC Package Number M20B N20A N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram © 1999 Fairchild Semiconductor Corporation DS010267 www.fairchildsemi.com 74F640 74F645 Unit Loading/Fan Out Pin Names OE T/R A0–A7 B0–B7 Description Output Enable Input (Active LOW) Transmit/Receive Input ...