74F598

INTEGRATED CIRCUITS 74F598 8-bit shift register with input storage registers (3-State) Product specification IC15 Data Handbook 1991 Oct 21 Philips Semiconductors Philips Semiconductors Product specification 8-bit shift register with input storage registers (3-State) 74F598 FEATURES High impedance PNP base input for reduced loading (20µA in High and Low states) 8–bit parallel storage register Shift register has asynchronous direct overriding reset Shift load SHLD is functional when SHCP is Low and locked out when SHCP is High. Guaranteed shift frequency DC to 105MHz Parallel 3–State I/O storage register inputs and shift register parallel outputs The shift register load function has been modified to load when both SHLD and SHCP are Low. When SHCP is High the shift register load operation is not performed. Data will be properly shifted on the rising edge of SHCP when SHLD is High. TYPE 74F598 TYPICAL SHCP fmax 100MHz TYPICAL SUPPLY CURRENT (TOTAL) 75mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F598N N74F598D PKG DWG # DESCRIPTION The 74F598 consists of an 8–bit storage register feeding a parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both the storage register and shift register have positive edge–triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous load. 20–pin plastic DIP 20–pin plastic SOL SOT146-1 SOT163-1 INPUT AND OUTPUT L...