74F544

www.DataSheet4U.com 74F544 Octal Registered Transceiver April 1988 Revised August 1999 74F544 Octal Registered Transceiver General Description The 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA. The 74F544 inverts data in both directions. Features s 8-bit octal transceiver s Back-to-back registers for storage s Separate controls for data flow in each direction s A outputs sink 24 mA, B outputs sink 64 mA Ordering Code: Order Number 74F544SC 74F544MSA 74F544SPC Package Number M24B MSA24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009555 www.fairchildsemi.com 74F544 Unit Loading/Fan Out U.L. Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0–A7 Description HIGH/LOW A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active ...