Document
74F382 4-Bit Arithmetic Logic Unit
May 1988 Revised August 1999
74F382 4-Bit Arithmetic Logic Unit
General Description
The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select input codes force the Function outputs LOW or HIGH. An Overflow output is provided for convenience in twos complement arithmetic. A Carry output is provided for ripple expansion. For high-speed expansion using a Carry Lookahead Generator, refer to the 74F381 data sheet.
Features
s Performs six arithmetic and logic functions s Selectable LOW (clear) and HIGH (preset) functions s LOW input loading minimizes drive requirements s Carry output for ripple expansion s Overflow output for twos complement arithmetic
Ordering Code:
Order Number 74F382SC 74F382SJ 74F382PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009529
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74F382
Unit Loading/Fan Out
Pin Names A0–A3 B0–B3 S0–S2 Cn Cn + 4 OVR F0–F3 Description A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Output Overflow Output Function Outputs U.L. HIGH/LOW 1.0/4.0 1.0/4.0 1.0/1.0 1.0/5.0 50/33.3 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−2.4 mA 20 µA/−2.4 mA 20 µA/−0.6 mA 20 µA/−3.0 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA
Functional Description
Signals applied to the Select inputs S0–S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 2. The overflow output OVR is the Exclusive-OR of Cn + 3 and Cn + 4; a HIGH signal on OVR indicates overflow in twos complement operation. Typical delays for Figure 2 are given in Figure 1.
Function Select Table
Select S0 L H L H L H L H
H = HIGH Voltage Level L = LOW Voltage Level
S1 L L H H L L H H
S2 L L L L H H H H
Operation Clear B Minus A A Minus B A Plus B A⊕B A+B AB Preset
Path Segment A1 or B1 to Cn + 4 Cn to Cn + 4 Cn to Cn + 4 Cn to F Cn to Cn + 4, OVR Total Delay
Toward F 6.5 ns 6.3 ns 6.3 ns 8.1 ns — 27.2 ns
Output Cn + 4, OVR 6.5 ns 6.3 ns 6.3 ns — 8.0 ns 27.1 ns
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Ripply Carry ALU Expansion
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2
74F382
Truth Table
Inputs Function CL.