74F259

INTEGRATED CIRCUITS 74F259 Latch Product specification IC15 Data Handbook 1989 Apr 11 Philips Semiconductors Philips Semiconductors Product specification Latch 74F259 FEATURES Combines demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as 1-of-8 active-High decoder DESCRIPTION The 74F259 addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the store mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data input, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs. PIN CONFIGURATION A0 1 A1 2 A2 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 8 16 V CC 15 MR 14 E 13 D 12 Q7 11 Q6 10 Q5 9 Q4 SF00823 TYPE TYPICAL PROPAGATION DELAY 7.5ns TYPICAL SUPPLY CURRENT (TOTAL) 31mA 74F2...