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74F240A Dataheets PDF



Part Number 74F240A
Manufacturers Philips
Logo Philips
Description Octal inverter buffer
Datasheet 74F240A Datasheet74F240A Datasheet (PDF)

INTEGRATED CIRCUITS 74F240/74F240A Octal inverter buffer (3-State) 74F241/74F241A Octal buffer (3-State) Product specification IC15 Data Handbook 1001 Jan 02 Philips Semiconductors Philips Semiconductors Product specification Buffers 74F240/74F240A/ 74F241/74F241A FEATURES • Octal bus interface • 3-State buffer outputs sink 64mA • 15mA source current • Guaranteed output skew less than 2.0ns (74F240A/74F241A) • Reduced ground bounce (74F240A/74F241A) DESCRIPTION The 74F240 and 74F241 are.

  74F240A   74F240A



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INTEGRATED CIRCUITS 74F240/74F240A Octal inverter buffer (3-State) 74F241/74F241A Octal buffer (3-State) Product specification IC15 Data Handbook 1001 Jan 02 Philips Semiconductors Philips Semiconductors Product specification Buffers 74F240/74F240A/ 74F241/74F241A FEATURES • Octal bus interface • 3-State buffer outputs sink 64mA • 15mA source current • Guaranteed output skew less than 2.0ns (74F240A/74F241A) • Reduced ground bounce (74F240A/74F241A) DESCRIPTION The 74F240 and 74F241 are octal buffers that are ideal for driving bus lines of buffer memory address registers. The outputs are all capable of sinking 64mA and sourcing up to 15mA. The device features two output enables, each controlling four of the 3–state outputs. The 74F240A and 74F241A are functionally equivalent to their non–A counterparts. They have been designed to reduce effects of ground noise. Other advantages are noted in the features. • Reduced ICC (74F241A only) • Reduced loading (74F240A IIL = 100µA, 74F241A IIL = 40µA) TYPE 74F240 74F240A 74F241 74F241A TYPICAL PROPAGATION DELAY 4.3ns 3.8ns 5.0ns 4.5ns TYPICAL SUPPLY CURRENT (TOTAL) 37mA 40mA 53mA 32mA ORDERING INFORMATION ORDER CODE DESCRIPTION 20–pin plastic DIP 20–pin plastic SOL 20-pin plastic SSOP II COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F240N, N74F240AN, N74F241N, N74F241AN N74F240D, N74F240AD, N74F241D, N74F241AD N74F240DB PKG DWG # SOT146-1 SOT163-1 SOT339-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS Data inputs (74F240) Ian, Ibn Data inputs (74F240A) Data inputs (74F241) Data inputs (74F241A) OEa, OEb Output enable inputs (active low) (74F240) Output enable inputs (active low) (74F240A) OEa, OEb Output enable input (74F241) Output enable input (74F241A) Yan, Ybn Data outputs (74F241, 74F241A) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.67 1.0/0.167 1.0/2.67 1.0/0.067 1.0/0.33 1.0/0.167 1.0/1.67 1.0/0.067 750/106.7 750/106.7 LOAD VALUE HIGH/LOW 20µA/1.0mA 20µA/100µA 20µA/1.6mA 20µA/40µA 20µA/0.2mA 20µA/100µA 20µA/1.0mA 20µA/40µA 15mA/64mA 15mA/64mA Yan, Ybn Data outputs (74F240, 74F240A) Note to input and output loading and fan out table One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. January 2, 1991 2 853–0355 01345 Philips Semiconductors Product specification Buffers 74F240/74F240A/ 74F241/74F241A PIN CONFIGURATION FOR 74F240/74F240A OEa Ia0 Yb0 Ia1 Yb1 Ia2 Yb2 Ia3 Yb3 1 2 3 4 5 6 7 8 9 20 VCC 19 OEb 18 Ya0 17 Ib0 16 Ya1 15 Ib1 14 Ya2 13 Ib2 IEC/IEEE SYMBOL FOR 74F240/74F240A 1 19 EN1 EN2 18 16 14 12 2 3 5 7 9 2 4 6 8 17 15 2D 1 12 Ya3 13 11 Ib3 11 GND 10 SF00320 SF00322 LOGIC SYMBOL FOR 74F240/74F240A 2 4 6 8 17 15 13 11 LOGIC DIAGRAM FOR 74F240/74F240A Ia0 2 18 Ya0 Ib0 17 3 Yb0 Ia0 1 19 OEa Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3 Ia1 4 16 Ya1 Ib1 15 5 Yb1 Ia2 OEb Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3 Ia3 6 14 Ya2 Ib2 13 7 Yb2 8 12 Ya3 Ib3 11 9 Yb3 18 VCC = Pin 20 GND = Pin 10 16 14 12 3 5 7 9 OEa 1 OEb 10 SF00321 VCC = Pin 20 GND = Pin 10 SF00323 FUNCTION TABLE FOR 74F240/74F240A INPUTS OEa L L H Ia L H X OEb L L H Ib L H X OUTPUTS Ya H L Z Yb H L Z Notes to function table for 74F240/74F240A H = High voltage level L = Low voltage level X = Don’t care Z = High impedance ”off” state January 2, 1991 3 Philips Semiconductors Product specification Buffers 74F240/74F240A/ 74F241/74F241A PIN CONFIGURATION FOR 74F241/74F241A OEa Ia0 Yb0 Ia1 Yb1 Ia2 Yb2 Ia3 Yb3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OEb Ya0 Ib0 Ya1 IEC/IEEE SYMBOL FOR 74F241/74F241A 1 19 EN1 EN2 18 16 14 12 2 3 5 7 9 2 4 6 2D 1 Ib1 Ya2 Ib2 Ya3 Ib3 8 17 15 13 11 SF00324 SF00326 LOGIC SYMBOL FOR 74F241/74F241A 2 4 6 8 17 15 13 11 LOGIC DIAGRAM FOR 74F241/74F241A Ia0 2 18 Ya0 Ib0 17 3 Yb0 Ia0 1 19 OEa Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3 Ia1 4 16 Ya1 Ib1 15 5 Yb1 Ia2 OEb Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3 Ia3 6 14 Ya2 Ib2 13 7 Yb2 8 12 Ya3 Ib3 11 9 Yb3 18 VCC = Pin 20 GND = Pin 10 16 14 12 3 5 7 9 OEa 1 OEb 10 SF00325 VCC = Pin 20 GND = Pin 10 SF00327 FUNCTION TABLE FOR 74F241/74F241A INPUTS OEa L L H Ia L H X OEb H H L Ib L H X OUTPUTS Ya L H Z Yb L H Z Notes to function table for 74F241/74F241A H = High voltage level L = Low voltage level X = Don’t care Z = High impedance ”off” state January 2, 1991 4 Philips Semiconductors Product specification Buffers 74F240/74F240A/ 74F241/74F241A ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Storage temperature range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to VCC 128 0 to +70 –65 to +150 UNIT V V mA V.


74F240 74F240A 74F241


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