74F225

INTEGRATED CIRCUITS 74F225 16X5 asynchronous FIFO (3-State) Product specification IC15 Data Handbook 1992 Jun 15 Philips Semiconductors Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 FEATURES Independent synchronous inputs and outputs Organized as 16 words of 5 bits DC to 25MHz data rate 3–State outputs Cascadable in word–width and depth direction DESCRIPTION This 80–bit active element First–In–First–Out (FIFO) is a monolithic Schottky–clamped transistor–transistor logic (STTL) array organized as 16–words of 5–bits each. A memory system using the ’F225 can be easily expanded in multiples of 16–words of 5–bits as shown in Figure 1. The 3–State outputs controlled by a single enable input (OE) make bus connection and multiplexing simple. The ’F225 processes data in a parallel format at any desired clock rate from DC to 25MHz. Status of the ’F225 is provided by three outputs, Input Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready (OR). The data outputs are non–inverting with respect to the data inputs and are disabled when the OE input is High. When OE is Low, the data outputs are enabled to function as totem–pole outputs. TYPICAL SUPPLY CURRENT ( TOTAL) 65mA TYPE 74F225 TYPICAL fMAX 25MHz ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F225N N74F225D PKG DWG # 20–pin plastic DIP 20–pin plastic SOL SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN OUT TAB...