74F192

74F192 Up/Down Decade Counter with Separate Up/Down Clocks April 1988 Revised March 1999 74F192 Up/Down Decade Counter with Separate Up/Down Clocks General Description The 74F192 is an up/down BCD decade (8421) counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are used as the clocks for a subsequent stage without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Features s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74F192SJ 74F192PC Package Number M16D N16E Package Description 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009496.prf www.fairchildsemi.com 74F192 Unit Loading/Fan Out U.L. Pin Names CPU CPD MR PL P0–P3 Q0–Q3 TCD TCU Description HIGH/LOW Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset In...