SDUD40N03L

S DU/D40N03L S amHop Microelectronics C orp. May,2004 ver1.1 N-C hannel Logic Level E nhancement Mode Field E ffect Transistor P R ODUC T S UMMAR Y V DS S 30V F E AT UR E S Max ID 42A R DS (ON) ( m W ) S uper high dense cell design for low R DS (ON ). 10 @ V G S = 10V 16 @ V G S = 4.5V R ugged and reliable. TO-252 and TO-251 P ackage. D D G S G D S G S DU S E R IE S TO-252AA(D-P AK) S DD S E R IE S TO-251(l-P AK) S ABS OLUTE MAXIMUM R ATINGS (T C =25 C unless otherwise noted) P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous -P ulsed a S ymbol V DS V GS @ TJ=125 C ID IDM IS PD T J , T S TG Limit 30 20 42 105 40 50 -55 to 175 Unit V V A A A W C Drain-S ource Diode Forward C urrent Maximum P ower Dissipation @ Tc=25 C Operating and S torage Temperature R ange THE R MAL C HAR AC TE R IS TIC S Thermal R esistance, Junction-to-C ase Thermal R esistance, Junction-to-Ambient 1 R JC R JA 3 50 C /W C /W S DU/D40N03L E LE CTR ICAL CHAR ACTE R IS TICS (T C =25 C unless otherwise noted) Parameter OFF CHAR ACTE R IS TICS Drain-S ource Breakdown Voltage Zero Gate Voltage Drain Current Gate-Body Leakage BV DS S IDS S IGS S V GS (th) R DS (ON) ID(ON) gFS C IS S C OS S CRSS b S ymbol Condition V GS = 0V, ID = 250uA V DS = 24V, V GS = 0V V GS = 20V, V DS = 0V V DS = V GS , ID = 250uA V GS = 10V, ID =20A V GS = 4.5V, ID = 10A V DS = 10V, V GS = 10V V DS = 10V, ID = 20A Min Typ Max Unit 30 10 V uA 100 nA 1 1.5 9 13 40 30 1375 670 200 3 10 1...