MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/1...
