Document
INTEGRATED CIRCUITS
DATA SHEET
SAA2510 Video CD (VCD) decoder
Preliminary specification File under Integrated Circuits, IC02 1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
FEATURES (With standard microcode loaded) • Decoding and display of MPEG1 video streams (constrained parameters) • Decoding of MPEG audio streams (layer II) • Decoding, storage (compressed) and display of high-resolution still pictures of 704 × 576 pixels • Requires only 4 Mbits of external 70 ns DRAM • Audio transparency mode for CD-DA discs • On-screen display capability • Play options: – Play – Stop – Pause/continue – Slow-motion forward – Scan forward – Scan backward. • Supports auto-pause feature • Disc interface: Philips I2S, EIAJ, MEC formats and IEC 958 (EBU) interface • Separate error flag input (EFIN) and data valid input (NDAV) • Performs basic block decoder functions: – serial-to-parallel conversion – sync detection – descrambling – EDC calculation – error-correction for mode 2 form 1 sectors – header and sub-header interpretation. • I2C-bus interface • Video output YUV 4 : 2 : 2 format. DMSD bus compatible • Also supports CCIR656 video interface, including line and field timing codes • Audio output: 44.1 kHz. 16, 18 or 20 bits per audio sample in Philips I2S, Sony or MEC formats ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA2510 QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 × 20 × 2.7 mm; high stand-off height 2 APPLICATION • Dedicated video CD players. GENERAL DESCRIPTION
SAA2510
• EBU audio output, fully transparent from input to output in CD-DA mode and generated in MPEG mode • Downloadable microcode for internal controllers • Internal video timing generator • Requires 40 MHz crystal for system clock generation • Requires 27 MHz crystal or external 27 MHz source for video timing generation • Requires 16.9344 MHz (384 × 44.1 kHz) clock locked to CD drive • Internal generation of 90 kHz MPEG clock • Capability of sharing external DRAM by 3-stating all DRAM pins.
MPEG1 audio and video CD (VCD) decoder, intended for use in low-cost dedicated video CD players. When used with a 4 Mbit DRAM and a digital video encoder, the decoder adds the required functionality to a CD decoder to implement a low-cost video CD player capable of playing discs coded to version 2.0 of the video CD specification. The SAA2510 is an I2C-bus controlled chip and features serial data input in four common bus formats. It provides digital video output in CCIR601 and 656 formats. A bit-mapped on-screen display is provided and output video timing can be 525 lines/30 frames per second or 625 lines/25 frames per second. The chip is microcode programmable for feature enhancement.
VERSION SOT317-1
1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
QUICK REFERENCE DATA SYMBOL VDD3 VDD5 IDD fxtal s fxtal v fi Tamb PARAMETER supply voltage supply voltage supply current system clock crystal frequency video clock crystal frequency audio clock input frequency operating ambient temperature MIN. 3.0 4.5 − − − − −20 3.3 5.0 tbf 40.0 27.0 16.9344 − TYP.
SAA2510
MAX. 3.6 5.5 − − − − +70 V V
UNIT
mA MHz MHz MHz °C
1996 May 21
3
andbook, full pagewidth
1996 May 21
EXTERNAL 4 Mbit DRAM OSD BUFFER 3k PLAY CONTROL BUFFER 7k Sys_osc_1 76 Sys_osc_0 74 RESET 27 W SYSTEM CLOCK EBUIN AUDIOCLK WSIN CLIN EFIN DAIN NDAV SDA SCL INT ASEL HOST I2C INTERFACE SYSTEM CONTROLLER BLOCK DECODER
BLOCK DIAGRAM
Philips Semiconductors
Video CD (VCD) decoder
AUDIO FIFO
VIDEO FIFO
VIDEO BUFFER 0
VIDEO BUFFER 1
VIDEO BUFFER 2
CAS RAS A0 to A8
CDIR DR0 to DR15 79 84
MEMORY MANAGEMENT UNIT VIDEO CLOCK
86 82 80
Vid_osc_0 Vid_osc_1 CLK27 CREF
VIDEO DECODER 8 8 DATA SORTER IDCT FRAME RECONSTRUCTOR VIDEO GENERATOR
7 to 1 100 95 to 88 99 97 11 9
UV0 to UV7 Y0 to Y7 VSYNC HREF TLSAND CSYNC
4
SAA2510
AUDIO DECODER TEST CONTROL 77 TP1 78 TP2 28
12 13 16 14
EBUOUT DAOUT CLOUT WSOUT
Preliminary specification
MGE325
DRAMON
SAA2510
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
PINNING SYMBOL UV6 PIN 1 video UV bus output bit 6; DESCRIPTION
SAA2510
16-bit video output mode: the UV bus outputs alternating U and V chroma samples at 13.5 Mbytes/s CCIR656 mode: this bus is not used (inactive) UV5 UV4 UV3 UV2 UV1 UV0 VDD5 CSYNC VSS5 TLSAND EBUOUT DAOUT WSOUT VDD3 CLOUT VSS AUDIOCLK VDD5 EBUIN CLIN WSIN DAIN VDD3 EFIN VSS RESET DRAMON INT NDAV ASEL SDA VDD5 SCL VSS5 DR15 1996 May 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 video UV bus bit 5 video UV bus bit 4 video UV bus bit 3 video UV bus bit 2 video UV bus bit 1 video UV bus bit 0 5 V external pad power supply composite sync output; 525 lines/60 Hz or 625 lines/50 Hz 0 V external pad power supply two-level Sandcastle (composite blanking) output; requires external resistor network to define horizontal/vertical bl.