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SAA2022 Dataheets PDF



Part Number SAA2022
Manufacturers Philips
Logo Philips
Description Tape formatting and error correction for the DCC system
Datasheet SAA2022 DatasheetSAA2022 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET SAA2022 Tape formatting and error correction for the DCC system Product specification Supersedes data of February 1993 File under Integrated Circuits, Miscellaneous February 1994 Philips Semiconductors Philips Semiconductors Product specification Tape formatting and error correction for the DCC system FEATURES • Integrated error correction encoder/decoder function with Digital Compact Cassette (DCC) optimized algorithms • Control of capstan servo during recordi.

  SAA2022   SAA2022


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INTEGRATED CIRCUITS DATA SHEET SAA2022 Tape formatting and error correction for the DCC system Product specification Supersedes data of February 1993 File under Integrated Circuits, Miscellaneous February 1994 Philips Semiconductors Philips Semiconductors Product specification Tape formatting and error correction for the DCC system FEATURES • Integrated error correction encoder/decoder function with Digital Compact Cassette (DCC) optimized algorithms • Control of capstan servo during recording and after recording by microcontroller • Frequency and phase regulation of capstan servo during playback • Choice of two Dynamic Random Access Memory (DRAM) types operating in page mode • Scratch pad RAM area available to microcontroller in system DRAM • Low power standby mode • I2S interface • Microcontroller interface for high-speed transfer burst rates up to 170 kbytes per second • SYSINFO and AUXILIARY data flags on microcontroller interface • Protection against invalid AUXILIARY data • +4 V operating voltage capability. ORDERING INFORMATION EXTENDED TYPE NUMBER SAA2022GP Note 1. PACKAGE PINS 64 PIN POSITION QFP (1) SAA2022 GENERAL DESCRIPTION Performing the tape formatting and error correction functions for DCC applications, the SAA2022 can be used in conjunction with the PASC (SAA2002/SAA2012), tape equalization (SAA2032), read amplifier (TDA1317 or TDA1318) and write amplifier (TDA1316 or TDA1319) circuits to implement a full signal processing system. MATERIAL plastic CODE SOT208A When using reflow soldering it is recommended that the Dry Packing instructions in the “Quality Reference Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011. February 1994 2 February 1994 3 BLOCK DIAGRAM Philips Semiconductors Tape formatting and error correction for the DCC system V DD1 LTCLK LTEN LTCNT1 LTCNT0 PINI SBEF SBDA SBCL SBWS SBMCLK TCH0 - 7, TAUX 5 6 3 4 49 57 62 61 60 56 33–41 43 V DD2 8 V DD3 27 V DD4 59 2 29 28 32 TAPE INPUT BUFFER TAPE OUTPUT BUFFER SB – I 2 S INTERFACE MICROCONTROLLER INTERFACE 50 51 LTDATA WDATA WCLOCK PINO1 PINO2 PINO3 ERROR CORRECTION CODER SAA2022 9 15 17–25 RASN CASN A0–8 CLOCK GENERATOR CONTROL DRAM INTERFACE 11–14 D0–3 10 16 WEN OEN LTREF URDA SBDIR SPEED SPDF RESET PWRDWN CLK24 48 47 44 1 64 63 30 31 52 55 42 V SS1 7 V SS2 26 V SS3 58 V SS4 Product specification AZCHK MCLK SAA2022 MEA711 - 2 Fig.1 Block diagram. Philips Semiconductors Product specification Tape formatting and error correction for the DCC system PINNING SYMBOL LTREF LTDATA LTCNT1 LTCNT0 LTCLK LTEN VSS2 VDD2 RASN WEN D3 D2 D1 D0 CASN OEN A8 A7 A6 A5 A4 A3 A2 A1 A0 VSS3 VDD3 WCLOCK WDATA SPEED SPDF PINO1 TAUX TCH7 TCH6 TCH5 TCH4 TCH3 TCH2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 DESCRIPTION timing reference for microcontroller interface data for microcontroller interface (3-state; CMOS levels) control for microcontroller interface control for microcontroller interface bit clock for microcontroller interface enable for microcontroller interface supply ground (0 V) supply voltage (+5 V) DRAM row address strobe DRAM write enable DRAM data (MSB); 3-state output; TTL compatible input DRAM data; 3-state output; TTL compatible input DRAM data; 3-state output; TTL compatible input DRAM data (LSB); 3-state output; TTL compatible input DRAM column address strobe DRAM output enable DRAM address (MSB) DRAM address DRAM address DRAM address DRAM address DRAM address DRAM address DRAM address DRAM address (LSB) supply ground (0 V) supply voltage (+5 V) clock for write amplifier transfers write amplifier serial data capstan phase information capstan frequency information Port expander output 1 AUX channel input from SAA2032 main data channel 7, input from SAA2032 main data channel 6, input from SAA2032 main data channel 5, input from SAA2032 main data channel 4, input from SAA2032 main data channel 3, input from SAA2032 main data channel 2, input from SAA2032 SAA2022 February 1994 4 Philips Semiconductors Product specification Tape formatting and error correction for the DCC system SYMBOL TCH1 TCH0 VSS1 VDD1 CLK24 TEST0 TEST1 PWRDWN RESET PINI PINO2 PINO3 AZCHK TEST2 TEST3 MCLK SBMCLK SBEF VSS4 VDD4 SBWS SBCL SBDA SBDIR URDA PIN 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DESCRIPTION main data channel 1, input from SAA2032 main data channel 0, input from SAA2032 supply ground (0 V) supply voltage (+5 V) 24.576 MHz clock from SAA2002 test select LSB; do not connect test select MSB; do not connect sleep mode selection reset input with hysteresis and pull-down resistor Port expander input Port expander output 2 Port expander output 3 azimuth check (channels 0 and 7) symbol error rate measurement output do not connect master clock output (6.144 MHz) master clock for SB-I2S-interface byte error SB-I2S-interface supply ground (0 V) supply voltage (+5 V) word select SB-I2S-int.


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