SA9101

sames FEATURES n Frame alignment/synthesis for PCM30 double frame and CRC-multiframe format. n n n SA9101 PCM FRAME ALIGNER Error counters for code errors (switchable to "Si zeros counter"), frame errors and CRC4 errors Sub-multiframe assigned CRC Error indication with possibility of automatic insertion in Si-bit position of outgoing multiframe. Simplified data transfer between SA9101 and controller, supported by data stacks for receive and transmit signalling data, selectable interruptsources and DMA facilities. Double frame marker for serial data extraction support Repeated transmission of signalling data, if not updated. Three transparent modes for timeslot 0 in transmit direction Transparent mode for receive direction HDB3 error indication Idle channel data insertion selectable for any timeslot Channel loopback capabilities, test and diagnostic capabilities Parity checks Meets CCITT Rec.G704 Interface to route selectable between HDB3 and fibre optical HDB3 outputs switchable between fully bauded and half bauded format Error checking via CRC4 procedure Insertion and extraction of alarms and facility signals Selectable system - clock (4096 kHz/ 8192 kHz) Selectable Interface mode (2048/4096 kBit/s) to system internal highway Programmable offsets for receive and transmit data Two frame receive buffer for receive route clock wander and jitter compensation Slip detection and direction indication Extended HDB3 error detection n n n n n n n n n n n n n n n n n n ...