Document
Bulletin I27125
rev. A 04/99
P100 SERIES
PASSIVATED ASSEMBLED CIRCUIT ELEMENTS
Features
Glass passivated junctions for greater reliability Electrically isolated base plate Available up to 1200 V RRM, V DRM High dynamic characteristics Wide choice of circuit configurations Simplified mechanical design and assembly UL E78996 approved
25A
Description
The P100 series of Integrated Power Circuits consists of power thyristors and power diodes configured in a single package. With its isolating base plate, mechanical designs are greatly simplified giving advantages of cost reduction and reduced size. Applications include power supplies, control circuits and battery chargers.
Major Ratings and Characteristics
Parameters
ID @ TC IFSM @ 50Hz @ 60Hz It
2
P100
25 85 357 375 637 580 6365 400 to 1200 2500 - 40 to 125
Units
A °C A A A 2s A 2s A2√s V V °C
@ 50Hz @ 60Hz
I2√ t VRRM VINS TJ
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P100 Series
Bulletin I27125 rev. A 04/99
ELECTRICAL SPECIFICATIONS Voltage Ratings
Type number VRRM maximum repetitive VRSM maximum nonVDRM maximum peak reverse voltage repetitive peak reverse repetitive peak off-state voltage voltage V V V
400 600 800 1000 1200 500 700 900 1100 1300 400 600 800 1000 1200
IRRM max.
@ TJ max.
mA
10
P101, P121, P131 P102, P122, P132 P103, P123, P133 P104, P124, P134 P105, P125, P135
On-state Conduction
Parameter
ID I TSM I FSM Maximum DC output current Max. peak one-cycle non-repetitive on-state or forward current
P100
25 357 375 300 315
Units Conditions
A @ TC = 85°C, full bridge t = 10ms A t = 8.3ms t = 10ms t = 8.3ms t = 10ms A s
2
No voltage reapplied 100% VRRM reapplied No voltage reapplied 100% VRRM reapplied Sinusoidal half wave, Initial TJ = TJ max.
I t
2
Maximum I t for fusing
2
637 580 450 410
t = 8.3ms t = 10ms t = 8.3ms
I 2√ t
Maximum I2 √t for fusing
6365
A2√s
t = 0.1 to 10ms, no voltage reapplied I 2t for time tx = I 2√t . √ tx
V T(TO) Max. value of threshold voltage r t1 Max. level value of on-state slope resistance V TM V FM di/dt Max. peak on-state or forward voltage drop Maximum non repetitive rate of rise of turned on current IH IL Maximum holding current Maximum latching current
0.82 12
V mΩ
TJ = 125°C TJ = 125°C, Av. power = VT(TO) * IT(AV) + rt + (IT(RMS)) 2
1.35
V
TJ = 25°C, ITM = π x I T(AV) TJ = 125°C from 0.67 VDRM ITM = π x IT(AV), I g = 500mA, tr < 0.5µs, tp > 6µs TJ = 25°C anode supply = 6V, resistive load, gate open TJ = 25°C anode supply = 6V, resistive load
200 130 250
A/µs mA mA
2
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P100 Series
Bulletin I27125 rev. A 04/99
Blocking
Parameter
dv/dt Maximum critical rate of rise of 200 off-state voltage IRRM IDRM IRRM VINS Max. peak reverse and off-state leakage current at VRRM, VDRM Max peak reverse leakage current 10 100 mA µA TJ = 125°C, gate open circuit TJ = 25°C 50Hz, circuit to base, all terminal shorted, RMS isolation voltage 2500 V TJ = 25°C, t = 1s V/µs TJ = 125°C, exponential to 0.67 VDRM gate open
P100
Units Conditions
Triggering
Parameter
PGM IGM - VGM Maximum peak gate power
P100
8 2 2 10 3 2 1
Units Conditions
W A
PG(AV) Maximum average gate power Maximum peak gate current Maximum peak negative gate voltage VGT Maximum gate voltage required to trigger
V
T J = - 40°C T J = 25°C T J = 125°C T J = - 40°C Anode Supply = 6V resistive load
IGD
Maximum gate current required to trigger
90 60 35 mA
T J = 25°C T J = 125°C
Anode Supply = 6V resistive load
VGD
Maximum gate voltage that will not trigger 0.2 V TJ = 125°C, rated VDRM applied
IGD
Maximum gate current that will not trigger 2 mA TJ = 125°C, rated VDRM applied
Thermal and Mechanical Specification
Parameter
TJ T
stg
P100
-40 to 125
Units
°C
Conditions
Max. operating temperature range Max. storage temperature range
-40 to 125 2.24 K/W DC operation per junction
RthJC Max. thermal resistance, junction to case RthCS Max. thermal resistance, case to heatsink T Mounting torque, base to heatsink
0.10
K/W
Mounting surface, smooth and greased
A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound
4
Nm
wt
Approximate weight
58 (2.0)
g (oz)
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P100 Series
Bulletin I27125 rev. A 04/99
Circuit Type and Coding *
Circuit "0"
Terminal Positions
Circuit "2"
Circuit "3"
G1
G1
G2
G3 AC1 AC2
G1
Schematic diagram diagram
AC1 AC2
AC2
AC1
G2
G4
G2
(-)
(+)
(-)
(+)
(-)
(+)
Single Phase Hybrid Bridge CommonCathode Basic series With voltage suppression With free-wheeling diode With both voltage suppression and free-wheeling diode P10. P10.K P10.W
Single Phase Hybrid Bridge Doubler P12. P12.K -
Single Phase All SCR Bridge P13. P13.K -
P10.KW
-
-
* To complete code refer to voltage ratings table, i.e.: for 600V P10.W complete code is P102W
Outline Table
4.6 (0.18)
12.7 (0.50) 12.7 (0.50)
1.65 (0.06)
4.6 (0.18)
2.5 (0.10) MAX .
15.5 (0.61)
63.5 (2.50) Faston 6.35x0.8 (0.25x 0.03)
5.2 (0.20)
45 (1.77)
33.8 (1.33) 48.7 (1..