June 1997
NDS332P P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel l...
June 1997
NDS332P P-Channel Logic Level Enhancement Mode Field Effect
Transistor
General Description
These P-Channel logic level enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
Features -1 A, -20 V, RDS(ON) = 0.41 Ω @ VGS= -2.7 V RDS(ON) = 0.3 Ω @ VGS = -4.5 V.
Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.0V.
Proprietary package design using copper lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and...