July 1996
NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel lo...
July 1996
NDS331N N-Channel Logic Level Enhancement Mode Field Effect
Transistor
General Description
These N-Channel logic level enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.
Features
1.3 A, 20 V. RDS(ON) = 0.21 Ω @ VGS= 2.7 V RDS(ON) = 0.16 Ω @ VGS= 4.5 V. Industry standard outline SOT-23 surface mount package using poprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability.
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Absolute Maximum Ratings
Symbol VDSS VGSS ID PD TJ,TSTG Parameter Drain-Source Voltage
T A = 25°C unless otherwise noted
NDS331N 20 8
(Note 1a)
Units V V A W
Gate-Source Voltage - Continuous Maximum Drain Current - Continuous - Pulsed Maximum Power Dissipation
(Note 1a) (Note 1b)
1.3 10 0.5 0.46 -55 to 150
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
(Note 1)
°C/W...