March 1996
NDC7001C Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N and P-...
March 1996
NDC7001C Dual N & P-Channel Enhancement Mode Field Effect
Transistor
General Description
These dual N and P-channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been designed to minimize on-state resistance, provide rugged and reliable performance and fast switching. These devices is particularly suited for low voltage, low current, switching, and power supply applications.
Features
N-Channel 0.51A, 50V, RDS(ON) = 2Ω @ VGS=10V P-Channel -0.34A, -50V. RDS(ON)= 5Ω @ VGS=-10V. High density cell design for low RDS(ON). Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High saturation current.
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4
3
5
2
6
SuperSOTTM-6
1
Absolute Maximum Ratings
Symbol VDSS VGSS ID Parameter Drain-Source Voltage
T A = 25°C unless otherwise noted
N-Channel 50 20
(Note 1a)
P-Channel -50 -20 -0.34 -1 0.96 0.9 0.7 -55 to 150
Units V V A
Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed
0.51 1.5
PD
Maximum Power Dissipation
(Note 1a) (Note 1b) (Note 1c)
W
TJ,TSTG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
130 60
°C/W °C/W
© 1997 Fairchild Semiconductor...