June1996
NDC632P P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel log...
June1996
NDC632P P-Channel Logic Level Enhancement Mode Field Effect
Transistor
General Description
These P-Channel logic level enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
Features
-2.7A, -20V. RDS(ON) = 0.14Ω @ VGS = -4.5V RDS(ON) = 0.2Ω @ VGS = -2.7V. Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability.
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4
3
5
2
6
1
SuperSOT -6
TM
Absolute Maximum Ratings
Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation
T A = 25°C unless otherwise noted
NDC632P -20 -8 -2.7 -10
(Note 1a) (Note 1b) (Note 1c)
Units V V A
1.6 1 0.8 -55 to 150
W
TJ,TSTG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junc...