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1345FAPC Dataheets PDF



Part Number 1345FAPC
Manufacturers Agere Systems
Logo Agere Systems
Description 1345-Type Receiver with Clock Recovery and Data Retiming
Datasheet 1345FAPC Datasheet1345FAPC Datasheet (PDF)

Data Sheet January 2000 1345-Type Receiver with Clock Recovery and Data Retiming Applications s Telecommunications: — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks High-speed data communications s Operating at 1.3 µm or 1.55 µm wavelengths and at 155 Mbits/s or 622 Mbits/s, the versatile 1345-Type Receiver is manufactured in a 20-pin, plastic DIP with a multimode fiber pigtail. Description The 1345-Type fiber-optic receiver is designed for use in tran.

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Data Sheet January 2000 1345-Type Receiver with Clock Recovery and Data Retiming Applications s Telecommunications: — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks High-speed data communications s Operating at 1.3 µm or 1.55 µm wavelengths and at 155 Mbits/s or 622 Mbits/s, the versatile 1345-Type Receiver is manufactured in a 20-pin, plastic DIP with a multimode fiber pigtail. Description The 1345-Type fiber-optic receiver is designed for use in transmission systems or medium- to highspeed data communication applications. Used in intermediate- and long-reach applications, the receiver operates at the SONET OC-3 or OC-12 data rate as well as the ITU-T synchronous digital hierarchy (SDH) rate of STM-1 or STM-4, depending on the receiver model chosen. The receiver meets all present Telcordia Technologies GR-253-CORE requirements, the current ANSI T1X1.5 intraoffice specifications, and the ITU-T G.957 and G.958 recommendations. Compact packaging, a high level of integration, and a wide dynamic range make these receivers ideal for data communications. Manufactured in a 20-pin DIP, the receiver consists of a planar InGaAs PIN photodetector, a silicon preamplifier, a silicon bipolar limiting amplifier that converts the small signal to ECL levels, a timing recovery unit to recover the clock, and a silicon bipolar decision circuit. Features s s s s Backward compatible with 1330 family Space-saving, self-contained, 20-pin plastic DIP Silicon based ICs Single 5 V power supply operation including photocurrent monitor capability Exceeds all SONET (GR-253-CORE) and ITU-T G.958 jitter requirements Clocked decision circuit Regenerated differential clock signal Wide dynamic range Qualified to meet the intent of Telcordia Technologies ™ reliability practices Operates at data rates of 155 Mbits/s or 622 Mbits/s Positive ECL (PECL) data outputs CMOS (TTL) link-status flag output Operation at 1.3 µm or 1.55 µm wavelengths Operating temperature range of –40 °C to +85 °C s s s s s s s s s s 1345-Type Receiver with Clock Recovery and Data Retiming Data Sheet January 2000 Description (continued) The receiver converts optical signals in the range of 1.1 µm to 1.6 µm into retimed clock and data signals. The clock and data outputs are raised-ECL (PECL) logic levels. A CMOS-level flag output indicates when there is a loss of optical signal. The receiver requires a 5 V power supply for the amplifier, logic, and PLL CRC circuits. The operating case temperature range is –40 °C to +85 °C. Flag Output When the optical input falls below the link status flag switching threshold, the link status flag is deactivated and its output logic level changes from a CMOS logic HIGH to a CMOS logic LOW. Squelched Data and Clock Outputs In some versions of the 1345 receiver (see Table 4), when the link status flag is deactivated, the data and clock outputs are squelched (stop outputting a signal). When this occurs, the DATA, DATA, CLOCK, and CLOCK outputs switch to a constant dc output voltage level of 1.3 V. Pin 10 Pin 10 on the 1345-Type receiver is not an internally connected (NIC) pin. This definition allows the 1345 to be used in most customer 20-pin receiver module applications. Customer’s printed-wiring boards that are designed with ground, +5 V, –5 V, or no connection to this pin are all acceptable options. For those applications that require monitoring the photocurrent of the PIN photodetector for power monitoring purposes, there are versions of the 1345 that require +5 V or –5 V applied to Pin 10. Check Tables 3 and 4 for ordering information. Nonsquelched Data and Clock Outputs Agere Systems also manufactures nonsquelching versions of the 1345 receiver for those applications that require the data and clock outputs to continue to function after the link status flag is deactivated. In those versions of the receiver, when the link status flag is deactivated, a signal will continue to appear at the DATA, DATA, CLOCK, and CLOCK outputs. See Table 4 for nonsquelching codes. OPTIONAL VPIN 5V FLAG FLAG DATA DATA FILTER InGaAs PIN Si PREAMPLIFIER SILICON BIPOLAR LIMITING AMPLIFIER SILICON BIPOLAR DECISION CIRCUIT PLL TIMING RECOVERY UNIT CLOCK CLOCK 1-724(C) Figure 1. Block Diagram 2 Agere Systems Inc. Data Sheet January 2000 1345-Type Receiver with Clock Recovery and Data Retiming Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Supply Voltage Operating Case Temperature Range Storage Case Temperature Range Lead Soldering Temperature/Time Operating Wavelength Range Minimum Fiber Bend Radius Symbol VCC TC Tstg — .


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