MM74HC148

MM74HC148 8-3 Line Priority Encoder October 1987 Revised February 1999 MM74HC148 8-3 Line Priority Encoder General Description The MM74HC148 priority encoder utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption typical of CMOS circuits, as well as the speeds and output drive similar to LB-TTL. This priority encoder accepts 8 input request lines 0–7 and outputs 3 lines A0–A2. The priority encoding ensures that only the highest order data line is encoded. Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. All data inputs and outputs are active at the low logic level. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s Typical propagation delay: 13 ns s Wide supply voltage range: 2V–6V Ordering Code: Order Number MM74HC148M MM74HC148MTC MM74HC148N Package Number M16A MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC and TSSOP Truth Table Inputs H X X X X X X X X H L H H H H H H H H H L X X X X X X X L L X X X X X X...