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83C51GB Dataheets PDF



Part Number 83C51GB
Manufacturers Intel Corporation
Logo Intel Corporation
Description CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Datasheet 83C51GB Datasheet83C51GB Datasheet (PDF)

8XC51GB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial Express 87C51GB 8 Kbytes OTP 8 Kbytes Internal Program Memory 83C51GB 8 Kbytes Factory Programmable ROM 80C51GB CPU with RAM and I O 8XC51GB 3 5 MHz to 12 MHz g 20% VCC 8XC51GB-1 3 5 MHz to 16 MHz g 20% VCC Y Y Y 8 Kbytes On-Chip ROM OTP ROM 256 Bytes of On-Chip Data RAM Two Programmable Counter Arrays with 2 x 5 High Speed Input Output Channels Compare Capture Pulse Width Modulators Watchdog Timer Capabilities Three 16-Bit Timer Counte.

  83C51GB   83C51GB



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8XC51GB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial Express 87C51GB 8 Kbytes OTP 8 Kbytes Internal Program Memory 83C51GB 8 Kbytes Factory Programmable ROM 80C51GB CPU with RAM and I O 8XC51GB 3 5 MHz to 12 MHz g 20% VCC 8XC51GB-1 3 5 MHz to 16 MHz g 20% VCC Y Y Y 8 Kbytes On-Chip ROM OTP ROM 256 Bytes of On-Chip Data RAM Two Programmable Counter Arrays with 2 x 5 High Speed Input Output Channels Compare Capture Pulse Width Modulators Watchdog Timer Capabilities Three 16-Bit Timer Counters with Four Programmable Modes Capture Baud Rate Generation (Timer 2) Dedicated Watchdog Timer 8-Bit 8-Channel A D with Eight 8-Bit Result Registers Four Programmable Modes Programmable Serial Channel with Framing Error Detection Automatic Address Recognition Serial Expansion Port Programmable Clock Out Extended Temperature Range ( b 40 C to a 85 C) Y 48 Programmable I O Lines with 40 Schmitt Trigger Inputs 15 Interrupt Sources with 7 External 8 Internal Sources 4 Programmable Priority Levels Pre-Determined Port States on Reset High Performance CHMOS Process TTL and CHMOS Compatible Logic Levels Power Saving Modes 64K External Data Memory Space 64K External Program Memory Space Three Level Program Lock System ONCE (ON-Circuit Emulation) Mode Quick Pulse Programming Algorithm MCS 51 Microcontroller Fully Compatible Instruction Set Boolean Processor Oscillator Fail Detect Available in 68-Pin PLCC Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y MEMORY ORGANIZATION PROGRAM MEMORY Up to 8 Kbytes of the program memory can reside in the on-chip ROM Also the device can address up to 64K of program memory external to the chip DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of external data memory The Intel 8XC51GB is a single-chip control oriented microcontroller which is fabricated on Intel’s CHMOS III-E technology The 8XC51GB is an enhanced version of the 8XC51FA and uses the same powerful instruction set and architecture as existing MCS 51 microcontroller products Added features make it an even more powerful microcontroller for applications that require On-Chip A D Pulse Width Modulation High Speed I O up down counting capabilities and memory protection features It also has a more versatile serial channel that facilitates multi-processor communications Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 November 1994 Order Number 272337-002 8XC51GB 272337 – 1 Figure 1 8XC51GB Block Diagram PROCESS INFORMATION This device is manufactured on P629 0 a CHMOS III-E process Additional process and reliability information is available in Intel’s Components Quality and Reliability Handbook Order No 210997 PACKAGES Part 8XC51GB Prefix N Package Type 68-Pin PLCC 2 8XC51GB PARALLEL I O PORTS The 8XC51GB contains six 8-bit parallel I O ports All six ports are bidirectional and consist of a latch an output driver and an input buffer Many of the port pins have multiplexed I O and control functions Port Pins as Inputs The pins of all six ports are configured as inputs by writing a logic 1 to them Since Port 0 is an open drain port it provides a very high input impedance Since pins of Port 1 2 3 4 and 5 have weak pullups (which are always on) they source a small current when driven low externally All ports except Port 0 have Schmitt trigger inputs Port Pins as Outputs Port 0 has open drain outputs when it is not serving as the external data bus The internal pullup is active only when the pin is outputting a logic 1 during external memory access An external pullup resistor is required on Port 0 when it is serving as an output port Ports 1 2 3 4 and 5 have quasi-bidirectional outputs A strong pullup provides a fast rise time when the pin is set to a logic 1 This pullup turns on for two oscillator periods to drive the pin high and then turns off The pin is held high by a weak pullup Writing the P0 P1 P2 P3 P4 or P5 Special Function Register sets the corresponding port pins All six port registers are bit addressable Port States During Reset Ports 0 and 3 reset asynchronously to a one and Ports 1 2 4 and 5 reset to a zero asynchronously PIN DESCRIPTIONS The 8XC51GB will be packaged in the 68-lead PLCC package Its pin assignment is shown in Figure 2 VCC Supply Voltage VSS Circuit Ground Diagram is for Pin Reference Only Package Size is Not to Scale OTP only 272337 – 2 Figure 2 Pin Connections 3 8XC51GB ALTERNATE PORT FUNCTIONS Ports 0 1 2 3 4 and 5 have alternate functions.


83C51FC 83C51GB 83C51KB


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